64Mb, 3V, Multiple I/O Serial Flash Memory
Features
Micron Serial NOR Flash Memory
3V, Multiple I/O, 4KB Sector Erase
N25Q064A
Features
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SPI-compatible serial bus interface
108 MHz (MAX) clock frequency
2.7–3.6V single supply voltage
Dual/quad I/O instruction provides increased
throughput up to 432 MHz
Supported protocols
– Extended SPI, dual I/O, and quad I/O
Execute-in-place (XIP) mode for all three protocols
– Configurable via volatile or nonvolatile registers
– Enables memory to work in XIP mode directly af-
ter power-on
PROGRAM/ERASE SUSPEND operations
Continuous read of entire memory via a single com-
mand
– Fast read
– Quad or dual output fast read
– Quad or dual I/O fast read
Flexible to fit application
– Configurable number of dummy cycles
– Output buffer configurable
64-byte, user-lockable, one-time programmable
(OTP) dedicated area
Erase capability
– Subsector erase 4KB uniform granularity blocks
– Sector erase 64KB uniform granularity blocks
– Full-chip erase
• Write protection
– Software write protection applicable to every
64KB sector via volatile lock bit
– Hardware write protection: protected area size
defined by five nonvolatile bits (BP0, BP1, BP2,
BP3, and TB)
– Additional smart protections, available upon re-
quest
• Electronic signature
– JEDEC-standard 2-byte signature (BA17h)
– Unique ID code (UID): 17 read-only bytes, in-
cluding:
• Two additional extended device ID (EDID)
bytes to identify device factory options
• Customized factory data (14 bytes)
• Minimum 100,000 ERASE cycles per sector
• More than 20 years data retention
• Packages JEDEC standard, all RoHS compliant
– F6 = V-PDFN-8 6mm x 5mm (MLP8 6mm x 5mm)
– F8 = V-PDFN-8 8mm x 6mm (MLP8 8mm x 6mm)
– 12 = T-PBGA-24b05 6mm x 8mm
– 14 = T-PBGA-24b05 6mm x 8mm, 4x6 ball array
– SF = SOP2-16 300 mils body width (SO16W)
– SE = SOP2-8 208 mils body width (SO8W)
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PDF: 09005aef845665f4
n25q_64mb_3v_65nm.pdf - Rev. K 08/13 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2011 Micron Technology, Inc. All rights reserved.
64Mb, 3V, Multiple I/O Serial Flash Memory
Features
Contents
Device Description ........................................................................................................................................... 6
Features ....................................................................................................................................................... 6
Operating Protocols ...................................................................................................................................... 6
XIP Mode ..................................................................................................................................................... 6
Device Configurability .................................................................................................................................. 7
Signal Assignments ........................................................................................................................................... 8
Signal Descriptions ......................................................................................................................................... 10
Memory Organization .................................................................................................................................... 12
Memory Configuration and Block Diagram .................................................................................................. 12
Memory Map – 64Mb Density ......................................................................................................................... 13
Device Protection ........................................................................................................................................... 14
Serial Peripheral Interface Modes .................................................................................................................... 16
SPI Protocols .................................................................................................................................................. 19
Nonvolatile and Volatile Registers ................................................................................................................... 20
Status Register ............................................................................................................................................ 21
Nonvolatile and Volatile Configuration Registers .......................................................................................... 22
Enhanced Volatile Configuration Register .................................................................................................... 24
Flag Status Register ..................................................................................................................................... 25
Command Definitions .................................................................................................................................... 27
READ REGISTER and WRITE REGISTER Operations ........................................................................................ 29
READ STATUS REGISTER or FLAG STATUS REGISTER Command ................................................................ 29
READ NONVOLATILE CONFIGURATION REGISTER Command ................................................................... 29
READ VOLATILE or ENHANCED VOLATILE CONFIGURATION REGISTER Command .................................. 30
WRITE STATUS REGISTER Command ......................................................................................................... 30
WRITE NONVOLATILE CONFIGURATION REGISTER Command ................................................................. 31
WRITE VOLATILE or ENHANCED VOLATILE CONFIGURATION REGISTER Command ................................. 31
READ LOCK REGISTER Command .............................................................................................................. 32
WRITE LOCK REGISTER Command ............................................................................................................ 33
CLEAR FLAG STATUS REGISTER Command ................................................................................................ 34
READ IDENTIFICATION Operations ............................................................................................................... 35
READ ID and MULTIPLE I/O READ ID Commands ...................................................................................... 35
READ SERIAL FLASH DISCOVERY PARAMETER Command ......................................................................... 36
READ MEMORY Operations ............................................................................................................................ 39
PROGRAM Operations .................................................................................................................................... 43
WRITE Operations .......................................................................................................................................... 48
WRITE ENABLE Command ......................................................................................................................... 48
WRITE DISABLE Command ........................................................................................................................ 48
ERASE Operations .......................................................................................................................................... 50
SUBSECTOR ERASE Command ................................................................................................................... 50
SECTOR ERASE Command ......................................................................................................................... 50
BULK ERASE Command ............................................................................................................................. 51
PROGRAM/ERASE SUSPEND Command ..................................................................................................... 52
PROGRAM/ERASE RESUME Command ...................................................................................................... 54
ONE TIME PROGRAMMABLE Operations ....................................................................................................... 55
READ OTP ARRAY Command ...................................................................................................................... 55
PROGRAM OTP ARRAY Command .............................................................................................................. 55
XIP Mode ....................................................................................................................................................... 58
Activate or Terminate XIP Using Volatile Configuration Register ................................................................... 58
Activate or Terminate XIP Using Nonvolatile Configuration Register ............................................................. 58
Confirmation Bit Settings Required to Activate or Terminate XIP .................................................................. 59
PDF: 09005aef845665f4
n25q_64mb_3v_65nm.pdf - Rev. K 08/13 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2011 Micron Technology, Inc. All rights reserved.
64Mb, 3V, Multiple I/O Serial Flash Memory
Features
Terminating XIP After a Controller and Memory Reset .................................................................................
Power-Up and Power-Down ............................................................................................................................
Power-Up and Power-Down Requirements ..................................................................................................
Power Loss Rescue Sequence ......................................................................................................................
AC Reset Specifications ...................................................................................................................................
Absolute Ratings and Operating Conditions .....................................................................................................
DC Characteristics and Operating Conditions ..................................................................................................
AC Characteristics and Operating Conditions ..................................................................................................
Package Dimensions .......................................................................................................................................
Part Number Ordering Information .................................................................................................................
Revision History .............................................................................................................................................
Rev. K – 08/2013 .........................................................................................................................................
Rev. J – 01/2013 ..........................................................................................................................................
Rev. I – 10/2012 ..........................................................................................................................................
Rev. H – 07/2012 .........................................................................................................................................
Rev. G – 06/2012 .........................................................................................................................................
Rev. F, Production – 10/2011 ........................................................................................................................
Rev. E, Production – 07/2011 .......................................................................................................................
Rev. D – 01/2011 .........................................................................................................................................
Rev. C – 11/2010 .........................................................................................................................................
Rev. B – 10/2010 .........................................................................................................................................
Rev. A – 05/2010 ..........................................................................................................................................
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PDF: 09005aef845665f4
n25q_64mb_3v_65nm.pdf - Rev. K 08/13 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2011 Micron Technology, Inc. All rights reserved.
64Mb, 3V, Multiple I/O Serial Flash Memory
Features
List of Figures
Figure 1: Logic Diagram ................................................................................................................................... 7
Figure 2: 8-Pin, VDFPN8 – MLP8 and SOP2 – SO8W (Top View) ......................................................................... 8
Figure 3: 16-Pin, Plastic Small Outline – SO16 (Top View) .................................................................................. 8
Figure 4: 24-Ball TBGA , 5 x 5 (Balls Down) ....................................................................................................... 9
Figure 5: 24-Ball TBGA, 4 x 6 (Balls Down) ........................................................................................................ 9
Figure 6: Block Diagram ................................................................................................................................ 12
Figure 7: Bus Master and Memory Devices on the SPI Bus ............................................................................... 17
Figure 8: Bus Master and Memory Devices on the SPI Bus ............................................................................... 18
Figure 9: SPI Modes ....................................................................................................................................... 18
Figure 10: Internal Configuration Register ...................................................................................................... 20
Figure 11: READ REGISTER Command .......................................................................................................... 29
Figure 12: WRITE REGISTER Command ......................................................................................................... 31
Figure 13: READ LOCK REGISTER Command ................................................................................................. 33
Figure 14: WRITE LOCK REGISTER Command ............................................................................................... 34
Figure 15: READ ID and MULTIPLE I/O Read ID Commands .......................................................................... 36
Figure 16: READ Command ........................................................................................................................... 40
Figure 17: FAST READ Command ................................................................................................................... 40
Figure 18: DUAL OUTPUT FAST READ ........................................................................................................... 41
Figure 19: DUAL INPUT/OUTPUT FAST READ Command .............................................................................. 41
Figure 20: QUAD OUTPUT FAST READ Command ......................................................................................... 42
Figure 21: QUAD INPUT/OUTPUT FAST READ Command ............................................................................. 42
Figure 22: PAGE PROGRAM Command .......................................................................................................... 44
Figure 23: DUAL INPUT FAST PROGRAM Command ...................................................................................... 45
Figure 24: EXTENDED DUAL INPUT FAST PROGRAM Command ................................................................... 45
Figure 25: QUAD INPUT FAST PROGRAM Command ..................................................................................... 46
Figure 26: EXTENDED QUAD INPUT FAST PROGRAM Command ................................................................... 47
Figure 27: WRITE ENABLE and WRITE DISABLE Command Sequence ............................................................ 49
Figure 28: SUBSECTOR and SECTOR ERASE Command .................................................................................. 51
Figure 29: BULK ERASE Command ................................................................................................................ 52
Figure 30: READ OTP Command .................................................................................................................... 55
Figure 31: PROGRAM OTP Command ............................................................................................................ 57
Figure 32: XIP Mode Directly After Power-On .................................................................................................. 59
Figure 33: Power-Up Timing .......................................................................................................................... 61
Figure 34: Reset AC Timing During PROGRAM or ERASE Cycle ........................................................................ 64
Figure 35: Reset Enable ................................................................................................................................. 64
Figure 36: Serial Input Timing ........................................................................................................................ 64
Figure 37: Write Protect Setup and Hold During WRITE STATUS REGISTER Operation (SRWD = 1) ................... 65
Figure 38: Hold Timing .................................................................................................................................. 65
Figure 39: Output Timing .............................................................................................................................. 66
Figure 40: V
PPH
Timing .................................................................................................................................. 66
Figure 41: AC Timing Input/Output Reference Levels ...................................................................................... 68
Figure 42: V-PDFN-8 6mm x 5mm (MLP8) – Package Code: F6 ........................................................................ 72
Figure 43: V-PDFN-8 8mm x 6mm (MLP8) – Package Code: F8 ........................................................................ 73
Figure 44: T-PBGA-24b05 6mm x 8mm – Package Code: 12 .............................................................................. 74
Figure 45: T-PBGA-24b05 6mm x 8mm – Package Code: 14 .............................................................................. 75
Figure 46: SOP2-16 (300 mils body width) – Package Code: SF ......................................................................... 76
Figure 47: SOP2-8 (208 mils body width) – Package Code: SE ........................................................................... 77
PDF: 09005aef845665f4
n25q_64mb_3v_65nm.pdf - Rev. K 08/13 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2011 Micron Technology, Inc. All rights reserved.
64Mb, 3V, Multiple I/O Serial Flash Memory
Features
List of Tables
Table 1: Signal Descriptions ...........................................................................................................................
Table 2: Sectors[127:0] ...................................................................................................................................
Table 3: Data Protection using Device Protocols .............................................................................................
Table 4: Memory Sector Protection Truth Table ..............................................................................................
Table 5: Protected Area Sizes – Upper Area .....................................................................................................
Table 6: Protected Area Sizes – Lower Area ......................................................................................................
Table 7: SPI Modes ........................................................................................................................................
Table 8: Extended, Dual, and Quad SPI Protocols ............................................................................................
Table 9: Status Register Bit Definitions ...........................................................................................................
Table 10: Nonvolatile Configuration Register Bit Definitions ...........................................................................
Table 11: Volatile Configuration Register Bit Definitions ..................................................................................
Table 12: Sequence of Bytes During Wrap .......................................................................................................
Table 13: Supported Clock Frequencies ..........................................................................................................
Table 14: Enhanced Volatile Configuration Register Bit Definitions ..................................................................
Table 15: Flag Status Register Bit Definitions ..................................................................................................
Table 16: Command Set .................................................................................................................................
Table 17: Lock Register ..................................................................................................................................
Table 18: Data/Address Lines for READ ID and MULTIPLE I/O READ ID Commands .......................................
Table 19: Read ID Data Out ............................................................................................................................
Table 20: Extended Device ID, First Byte .........................................................................................................
Table 21: Serial Flash Discovery Parameter – Header Structure ........................................................................
Table 22: Parameter ID ..................................................................................................................................
Table 23: Command/Address/Data Lines for READ MEMORY Commands .......................................................
Table 24: Data/Address Lines for PROGRAM Commands ................................................................................
Table 25: Suspend Parameters .......................................................................................................................
Table 26: Operations Allowed/Disallowed During Device States ......................................................................
Table 27: OTP Control Byte (Byte 64) ..............................................................................................................
Table 28: XIP Confirmation Bit .......................................................................................................................
Table 29: Effects of Running XIP in Different Protocols ....................................................................................
Table 30: Power-Up Timing and V
WI
Threshold ...............................................................................................
Table 31: AC RESET Conditions ......................................................................................................................
Table 32: Absolute Ratings .............................................................................................................................
Table 33: Operating Conditions ......................................................................................................................
Table 34: Input/Output Capacitance ..............................................................................................................
Table 35: AC Timing Input/Output Conditions ...............................................................................................
Table 36: DC Current Characteristics and Operating Conditions ......................................................................
Table 37: DC Voltage Characteristics and Operating Conditions ......................................................................
Table 38: AC Characteristics and Operating Conditions ...................................................................................
Table 39: Part Number Information ................................................................................................................
Table 40: Package Details ...............................................................................................................................
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PDF: 09005aef845665f4
n25q_64mb_3v_65nm.pdf - Rev. K 08/13 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2011 Micron Technology, Inc. All rights reserved.
