INTEGRATED CIRCUITS
74F132
Quad 2-input NAND Schmitt trigger
Product specification
IC15 Data Handbook
1991 Jun 26
Philips
Semiconductors
Philips Semiconductors
Product specification
Quad 2-input NAND Schmitt trigger
74F132
DESCRIPTION
The 74F132 contains four 2-input NAND gates which accept
standard TTL input signals and provide standard TTL output levels.
They are capable of transforming slowly changing input signals into
sharply defined, jitter-free output signals. In addition, they have
greater noise margin than conventional NAND gates. Each circuit
contains a 2-input Schmitt trigger followed by a Darlington level
shifter and a phase splitter driving a TTL totem-pole output. The
Scmitt trigger uses positive feedback to effectively speed-up slow
input transitions and provide different input threshold voltages for
positive and negative-going transitions. This hysteresis between the
positive-going and negative-going input threshold (typically 800mV)
is determined by resistor ratios and is essentially insensitive to
temperature and supply voltage variations. As long as three inputs
remain at a more positive voltage than V
T+MAX
, the gate will
respond in the transition of the other input as shown in Waveform 1.
PIN CONFIGURATION
D0a
D0b
Q0
D1a
D1b
Q1
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
D3b
D3a
Q3
D2b
D2a
Q2
SF00710
TYPE
TYPICAL
PROPAGATION
DELAY
6.3ns
TYPICAL
SUPPLY CURRENT
(TOTAL)
13mA
74F132
ORDERING INFORMATION
DESCRIPTION
14-pin plastic DIP
14-pin plastic SO
COMMERCIAL RANGE
V
CC
= 5V
±10%,
T
amb
= 0°C to +70°C
N74F132N
N74F132D
PKG DWG #
SOT27-1
SOT108-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
Dna, Dnb
Qn
DESCRIPTION
Data inputs
Data output
74F (U.L.) HIGH/LOW
1.0/1.0
50/33
LOAD VALUE HIGH/LOW
20µA/0.6mA
1.0mA/20mA
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOGIC SYMBOL
IEC/IEEE SYMBOL
1
&
3
1
2
4
5
9
10
12
13
2
4
D0a
D0b
D1a
D1b
D2a
D2b
D3a
D3b
5
9
6
Q0
Q1
Q2
Q3
8
10
3
6
8
11
12
11
13
V
CC
= Pin 14
GND = Pin 7
SF00711
SF00712
1991 Jun 26
2
853–0342 03094
Philips Semiconductors
Product specification
Quad 2-input NAND Schmitt trigger
74F132
LOGIC DIAGRAM
D0a
D0b
D1a
D1b
D2a
D2b
V
CC
= Pin 14
GND = Pin 7
D3a
D3b
1
2
4
5
9
10
12
13
11
3
Q0
FUNCTION TABLE
INPUTS
Dna
L
L
8
Q2
OUTPUT
Dnb
L
H
L
Qn
H
H
H
L
6
Q1
H
Q3
SF00002
H
H
NOTES:
H = High voltage level
L = Low voltage level
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limits set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage
Input voltage
Input current
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to V
CC
40
0 to +70
–65 to +150
UNIT
V
V
mA
V
mA
°C
°C
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
V
CC
I
IK
I
OH
I
OL
T
amb
Supply voltage
Input clamp current
High-level output current
Low-level output current
Operating free-air temperature range
0
PARAMETER
MIN
4.5
NOM
5.0
MAX
5.5
–18
–1
20
+70
UNIT
V
mA
mA
mA
°C
1991 Jun 26
3
Philips Semiconductors
Product specification
Quad 2-input NAND Schmitt trigger
74F132
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
V
T+
V
T–
nV
T
V
O
OH
PARAMETER
Positive-going threshold
Negative-going threshold–
Hysteresis (V
T+
– V
T–
)
High-level
High level output voltage
TEST CONDITIONS
1
V
CC
= 5.0V
V
CC
= 5.0V
V
CC
= 5.0V
V
CC
= MIN,
V
I=
V
T–MAX
, I
OH
= MAX
Low-level
Low level output voltage
Input clamp voltage
Input current at positive-going threshold
Input current at negative-going threshold
Input current at maximum input voltage
High-level input current
Low-level input current
Short-circuit output current
3
Supply current (total)
I
CCH
I
CCL
V
CC
= MIN,
V
I=
V
T+MAX
, I
OL
= MAX
V
CC
= MIN, I
I
= I
IK
V
CC
= 5.0V, V
I
=V
T+
V
CC
= 5.0V, V
I
=V
T–
V
CC
= MAX, V
I
= 7.0V
V
CC
= MAX, V
I
= 2.7V
V
CC
= MAX, V
I
= 0.5V
V
CC
= MAX
V
CC
= MAX
V
I N
= GND
V
IN
= 4.5V
–60
8.5
13.0
±10%V
CC
±5%V
CC
±10%V
CC
±5%V
CC
LIMITS
MIN
1.5
0.7
0.4
2.5
2.7
3.4
0.30
0.30
–0.73
0
–350
100
20
–0.6
–150
12.0
19.5
0.50
0.50
–1.2
V
µA
µA
µA
µA
mA
mA
mA
V
TYP
2
1.7
0.9
0.8
MAX
2.0
1.1
UNIT
V
V
V
V
V
O
OL
V
IK
I
T+
I
T–
I
I
I
IH
I
IL
I
OS
I
CC
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25°C.
3. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a High output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
1991 Jun 26
4
Philips Semiconductors
Product specification
Quad 2-input NAND Schmitt trigger
74F132
AC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
V
CC
= +5.0V
T
amb
= +25°C
C
L
= 50pF, R
L
= 500Ω
MIN
t
PLH
t
PHL
Propagation delay
Dna, Dnb to Qn
Waveform 1
3.5
4.5
TYP
5.5
6.0
MAX
7.0
8.5
V
CC
= +5.0V
±
10%
T
amb
= 0°C to +70°C
C
L
= 50pF, R
L
= 500Ω
MIN
3.0
4.5
MAX
8.5
9.0
ns
UNIT
AC WAVEFORMS
For all waveforms, V
M
= 1.5V.
Dna, Dnb
V
M
t
PHL
V
M
t
PLH
Qn
V
M
V
M
SF00005
Waveform 1. For Inverting Outputs
TEST CIRCUIT AND WAVEFORMS
V
CC
NEGATIVE
PULSE
V
IN
PULSE
GENERATOR
R
T
D.U.T.
V
OUT
90%
V
M
10%
t
THL (
t
f
)
C
L
R
L
t
w
V
M
10%
t
TLH (
t
r
)
0V
90%
AMP (V)
t
TLH (
t
r
)
90%
POSITIVE
PULSE
V
M
10%
t
w
t
THL (
t
f
)
AMP (V)
90%
V
M
10%
0V
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
R
L
= Load resistor;
see AC ELECTRICAL CHARACTERISTICS for value.
C
L
= Load capacitance includes jig and probe capacitance;
see AC ELECTRICAL CHARACTERISTICS for value.
R
T
= Termination resistance should be equal to Z
OUT
of
pulse generators.
Input Pulse Definition
INPUT PULSE REQUIREMENTS
family
amplitude V
M
74F
3.0V
1.5V
rep. rate
1MHz
t
w
500ns
t
TLH
2.5ns
t
THL
2.5ns
SF00006
1991 Jun 26
5
RF/无线
