INTEGRATED CIRCUITS
74F50729
Synchronizing dual D-type flip-flop
with edge-triggered set and reset and
metastable immune characteristics
Product data
Supersedes data of 1990 Sep 14
2003 Jan 20
Philips
Semiconductors
Philips Semiconductors
Product data
Synchronizing dual D-type flip-flop with edge-triggered
set and reset and metastable immune characteristics
74F50729
FEATURES
•
Metastable immune characteristics
•
Output skew less than 1.5 ns
•
High source current (I
OH
= 15 mA) ideal for clock driver
applications
PIN CONFIGURATION
RD0 1
D0 2
CP0 3
SD0 4
Q0 5
Q0 6
GND 7
14 V
CC
13
RD1
•
See 74F5074 for synchronizing dual D-type flip-flop
•
See 74F50109 for synchronizing dual J-K positive edge-triggered
flip-flop
12 D1
11
10
9
8
CP1
SD1
Q1
Q1
•
See 74F50728 for synchronizing cascaded dual D-type flip-flop
•
Industrial temperature range available (–40
°C
to +85
°C)
DESCRIPTION
The 74F50729 is a dual positive edge-triggered D-type featuring
individual data, clock, set and reset inputs; also true and
complementary outputs.
The 74F50729 is designed so that the outputs can never display a
metastable state due to setup and hold time violations. If setup time
and hold time are violated the propagation delays may be extended
beyond the specifications but the outputs will not glitch or display a
metastable state. Typical metastability parameters for the 74F50729
are:
τ ≅
135 ps and
τ ≅
9.8
×
10
6
sec, where
τ
represents a
function of the rate at which a latch in a metastable state resolves
that condition, and T
o
represents a function of the measurement of
the propensity of a latch to enter a metastable state.
Set (SDn) and reset (RDn) are asynchronous positive-edge
triggered inputs and operate independently of the clock (CPn) input.
Data must be stable just one setup time prior to the low-to-high
transition of the clock for guaranteed propagation delays.
Clock triggering occurs at a voltage level and is not directly related
to the transition time of the positive-going pulse. Following the hold
time interval, data at the Dn input may be changed without affecting
the levels of the output.
TYPE
74F50729
SF00611
TYPICAL f
MAX
120 MHz
TYPICAL SUPPLY
CURRENT (TOTAL)
19 mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
14-pin plastic DIP
14-pin plastic SO
COMMERCIAL RANGE
V
CC
= 5V
±10%,
T
amb
= 0
°C
to +70
°C
N74F50729N
N74F50729D
INDUSTRIAL RANGE
V
CC
= 5V
±10%,
T
amb
= –40
°C
to +85
°C
I74F50729N
I74F50729D
PKG DWG #
SOT27-1
SOT108-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
D0, D1
CP0, CP1
SD0, SD1
RD0, RD1
Data inputs
Clock inputs (active rising edge)
Set inputs (active rising edge)
Reset inputs (active rising edge)
DESCRIPTION
74F (U.L.)
HIGH/LOW
1.0/0.417
1.0/1.0
1.0/1.0
1.0/1.0
750/33
LOAD VALUE
HIGH/LOW
20
µA
/ 250
µA
20
µA
/ 20
µA
20
µA
/ 20
µA
20
µA
/ 20
µA
15 mA / 20 mA
Q0, Q1, Q0, Q1
Data outputs
NOTE:
One (1.0) FAST unit load is defined as: 20
µA
in the high state and 0.6 mA in the low state.
2003 Jan 20
2
Philips Semiconductors
Product data
Synchronizing dual D-type flip-flop with edge-triggered
set and reset and metastable immune characteristics
74F50729
LOGIC SYMBOL
IEC/IEEE SYMBOL
4
2
12
3
C1
D0 D1
2
1
S
&
3
3
4
1
11
10
13
CP0
SD0
RD0
CP1
SD1
RD1
Q0 Q0 Q1 Q1
1D
6
R
10
11
12
13
S
C2
2D
9
5
V
CC
= Pin 14
GND = Pin 7
6
9
8
8
R
SF00612
SF00613
METASTABLE IMMUNE CHARACTERISTICS
Philips Semiconductors uses the term ‘metastable immune’ to
describe characteristics of some of the products in its family.
Specifically the 74F50XXX family presently consist of 4 products
which will not glitch or display metastable immune characteristics.
This term means that the outputs will not glitch or display an output
anomaly under any circumstances including setup and hold time
violations. This claim is easily verified on the 74F5074. By running
two independent signal generators (see Fig. 1) at nearly the same
frequency (in this case 10 MHz clock and 10.02 MHz data) the
device-under-test can be often be driven into metastable state. If the
Q output is then used to trigger a digital scope set to infinite
persistence the Q output will build a waveform. An experiment was
run by continuously operating the devices in the region where
metastability will occur.
When the device-under-test is a 74F74 (which was not designed
with metastable immune characteristics) the waveform will appear
as in Fig. 2.
Figure 2 shows clearly that the Q output can vary in time with
respect to the Q trigger point. This also implies that the Q or Q
output waveshapes may be distorted. This can be verified on an
analog scope with a charge plate CRT. Perhaps of even greater
interest are the dots running along the 3.5V volt line in the upper
right hand quadrant. These show that the Q output did not change
state even though the Q output glitched to at least 1.5 volt, the
trigger point of the scope.
When the device-under-test is a metastable immune part, such as
the 74F5074, the waveform will appear as in Fig. 3. The 74F5074 Q
output will appear as in Fig. 3. The 74F5074 Q output will not vary
with respect to the Q trigger point even when the a part is driven into
a metastable state. Any tendency towards internal metastability is
resolved by Philips Semiconductors patented circuitry. If a
metastable event occurs within the flop the only outward
manifestation of the event will be an increased clock-to-Q/Q
propagation delay. This propagation delay is, of course, a function of
the metastability characteristics of the part defined by
τ
and T
0.
The metastability characteristics of the 74F5074 and related part
types represent state-of-the-art TTL technology.
After determining the T
0
and t of the flop, calculating the mean time
between failures (MTBF) is simple. Suppose a designer wants to
use the 74F50729 for synchronizing asynchronous data that is
arriving at 10 MHz (as measured by a frequency counter), has a
clock frequency of 50 MHz, and has decided that he would like to
sample the output of the 74F50729 10 nanoseconds after the clock
edge. He simply plugs his number into the equation below:
MTBF = e
(t’/t)
/ T
o
f
C
f
I
In this formula, f
C
is the frequency of the clock, f
I
is the average
input event frequency, and t’ is the time after the clock pulse that the
output is sampled (t’ < h, h being the normal propagation delay). In
this situation the f
I
will be twice the data frequency of 20 MHz
because input events consist of both of low and high transitions.
Multiplying f
I
by f
C
gives an answer of 10
15
Hz
2
. From Fig. 3. it is
clear that the MTBF is greater than 10
10
seconds. Using the above
formula the actual MTBF is 1.51
×
10
10
seconds or about 480 years.
SIGNAL GENERATOR
D
Q
TRIGGER
DIGITAL
SCOPE
SIGNAL GENERATOR
CP
Q
INPUT
SF00586
Figure 1. Test set-up
2003 Jan 20
3
Philips Semiconductors
Product data
Synchronizing dual D-type flip-flop with edge-triggered
set and reset and metastable immune characteristics
74F50729
COMPARISON OF METASTABLE IMMUNE AND NON-IMMUNE CHARACTERISTICS
4
3
2
1
0
Time base = 2.00ns/div Trigger level = 1.5 Volts Trigger slope = positive
SF00587
Figure 2. 74F74 Q output triggered by Q output, set-up and hold times violated
3
2
1
0
Time base = 2.00ns/div Trigger level = 1.5 Volts Trigger slope = positive
SF00588
Figure 3. 74F74 Q output triggered by Q output, set-up and hold times violated
2003 Jan 20
4
Philips Semiconductors
Product data
Synchronizing dual D-type flip-flop with edge-triggered
set and reset and metastable immune characteristics
74F50729
MEAN TIME BETWEEN FAILURES (MTBF) VERSUS t’
10
6
10
8
10
10
10
12
10
14
10
12
10
11
10,000 years
10
10
100 years
MTBF in seconds
10
8
one year
10
7
10
6
one week
7
8
9
10
SF00589
10
15
= f
C
f
I
10
9
t’ in nanoseconds
NOTE:
V
CC
= 5 V, T
amb
= 25
°C, τ
=135 ps, T
o
= 9.8
×
10
6
sec
Figure 4.
TYPICAL VALUES FOR
τ
AND T
0
AT VARIOUS V
CC
S AND TEMPERATURES
V
CC
5.5 V
5.0 V
4.5 V
T
amb
= 0
°C
τ
125 ps
115 ps
115 ps
T
0
1.0
×
10
9
sec
1.3
×
10
10
sec
3.4
×
10
13
sec
τ
138 ps
135 ps
132 ps
T
amb
= 25
°C
T
0
5.4
×
10
6
sec
9.8
×
10
6
sec
5.1
×
10
8
sec
τ
160 ps
167 ps
175 ps
T
amb
= 70
°C
T
0
1.7
×
10
5
sec
3.9
×
10
4
sec
7.3
×
10
4
sec
FUNCTION TABLE
INPUTS
SD
↑
↑
↑
↑
↑
RD
↑
↑
↑
↑
↑
CP
X
X
↑
↑
↑
D
X
X
h
l
X
OUTPUTS
Q
H
L
H
L
NC
Q
L
H
L
H
NC
OPERATING
MODE
Asynchronous set
Asynchronous reset
Load ”1”
Load ”0”
Hold
LOGIC DIAGRAM
SD
4, 10
RD
1, 13
5, 9
Q
CP
3, 11
6, 8
Q
NOTES:
1. H = High-voltage level
2. h = High-voltage level one set-up time prior to low-to-high clock
transition
3. L = Low-voltage level
4. l = Low-voltage level one set-up time prior to low-to-high clock
transition
5. NC= No change from the previous set-up
6. X = Don’t care
7.
↑
= Low-to-high clock transition
8.
↑
= Not low-to-high clock transition
2, 12
D
V
CC
= Pin 14
GND = Pin 7
SF00614
2003 Jan 20
5
