NANDxxxxNx
Large page NAND flash memory and
low power SDRAM, 1.8/2.6 V MCP and PoP
Features
FBGA
n
MCP (multichip package) and PoP (package
on package)
– NAND flash memory
– 1-, 2-, 4-, 2x2-Gbit large page size NAND
flash memory
– 256-, 512-, 2x512-, 128+256/512-Mbit or
1-Gbit (x16/x32) SDR/DDR LPSDRAM
Temperature range: -30 up to 85 °C
Supply voltage
– NAND flash: V
DDF
= 1.7-1.95 V or 2.5-3.6 V
– LPSDRAM: V
DDD
= V
DDQD
= 1.7-1.95 V
Electronic signature
ECOPACK
®
packages
TFBGA107 10.5 × 13 × 1.2 mm
TFBGA137 10.5 x 13 x 1.2 mm
LFBGA137 10.5 x 13 x 1.4 mm
TFBGA149 10 × 13.5 × 1.2 mm
VFBGA160 15 x 15 x 1 mm
FBGA
n
n
n
n
VFBGA152 14 x 14 x 0.9 mm
TFBGA152 14×14 × 1.1 mm
TFBGA152 14 × 14 × 1.2 mm
TFBGA128 12 x 12 x 1.1 mm
Flash memory
n
Single or double data rate LPSDRAM
n
n
n
n
n
n
n
Nand interface
– x8 or x16 bus width
– Multiplexed address/data
Page size
– x8 device: (2048 + 64 spare) bytes
– x16 device: (1024 + 32 spare) words
Block size
– x8 device: (128K + 4K spare) bytes
– x16 device: (64K + 2K spare) words
Page read/program
– Random access: 25 µs (max)
– Sequential access: 25/30 ns (min)
– Page program time: 200 µs (typ)
Copy back program mode
Fast block erase: 1.5/2 ms (typ)
Chip Enable ‘don’t care’
Status register
Data integrity
– 100 000 program/erase cycles
– 10 years data retention
Interface: x16/32 bus width
Deep power-down mode
1.8 V LVCMOS interface
Quad internal banks controlled by BA0, BA1
Wrap sequence: sequential/interleaved
Automatic and controlled precharge
Auto refresh and self refresh
– 8192 or 4096 (for 128 Mbits) refresh
cycles/64 ms
– Programmable partial array self refresh
– Auto temperature compensated self refresh
Device summary
NANDxxxxNx
NANDA8R3N0
NANDA9WxN1
NANDBAR4Nx
NANDB9R4Nx
NANDCAW4N1
NANDD3R4N5
NANDA9R3Nx
NANDB0R3N0
NANDB1R3N0
NANDC9R4N0
NANDCBR4N3
NANDDBR3N5
n
n
n
Table 1.
n
n
n
n
n
NANDA0R3N0
NANDA9R4Nx
NANDBAR3Nx
NANDB9R3N0
NANDBAW4N1
NANDC3R4N5
October 2008
Rev 12
1/52
www.numonyx.com
1
Contents
NANDxxxxNx
Contents
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16
2.17
2.18
2.19
2.20
2.21
2.22
2.23
2.24
2.25
2.26
Flash memory inputs/outputs (I/O0-I/O7) . . . . . . . . . . . . . . . . . . . . . . . . . 25
Flash memory inputs/outputs (I/O8-I/O15) . . . . . . . . . . . . . . . . . . . . . . . . 25
Flash memory Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . 25
Flash memory Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . 25
Flash memory Chip Enable (E
F
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Flash memory Read Enable (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Flash memory Write Enable (W
F
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Flash memory Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Flash memory Ready/Busy (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Flash memory V
DDF
supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
LPSDRAM Address inputs (A0-Ax) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
LPSDRAM Bank Select Address inputs (BA0-BA1) . . . . . . . . . . . . . . . . . 26
LPSDRAM Data inputs/outputs (DQ0-DQ31) . . . . . . . . . . . . . . . . . . . . . . 27
LPSDRAM Chip Select (E
D
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
LPSDRAM Column Address Strobe (CAS) . . . . . . . . . . . . . . . . . . . . . . . 27
LPSDRAM Row Address Strobe (RAS) . . . . . . . . . . . . . . . . . . . . . . . . . . 27
LPSDRAM Write Enable (W
D
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
LPSDRAM Clock Input (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
LPSDRAM Clock Input (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
LPSDRAM Clock Enable (KE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
LPSDRAM lower/upper data input/output mask (DQM0 to DQM3) . . . . . 28
DQS0 to DQS3 input/outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Lower/Upper Data Read/Write Strobe input/output (LDQS, UDQS) . . . . 28
LPSDRAM V
DDD
supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
LPSDRAM V
DDQD
supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.26.1
2.26.2
NANDxxxxNx devices delivered in TFBGA107/137/149 packages . . . . 29
NANDxxxxNx delivered in TFBGA128/152 and VFBGA160 packages . 29
2/52
NANDxxxxNx
Contents
3
4
5
6
7
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3/52
List of tables
NANDxxxxNx
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Product list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
TFBGA107 10.5 × 13 mm - 10 × 14 active ball array, 0.80 mm pitch,
mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
TFBGA128 - 2-row perimeter matrix 2R18 × 18, 12 × 12 mm, 0.65 mm pitch,
mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
TFBGA137 10.5 x 13 mm - 10 x 15-13 active ball array, 0.80 mm pitch,
mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
LFBGA137 10.5 x 13 x 1.4 mm - 10 x 15-13 active ball array, 0.80 mm pitch,
mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
TFBGA149 10 × 13.5 mm - 12 × 16 active ball array, 0.80 mm pitch, mechanical data. . . 43
TFBGA152, 2-row perimeter matrix 2R21 x 21, 14 x 14 x 1.1 mm, 0.65 mm pitch,
mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
TFBGA152, 2-row perimeter matrix 2R21 x 21, 14 x 14 x 0.9 mm, 0.65 mm pitch,
mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
TFBGA152, 2-row perimeter matrix 2R21 x 21, 14 × 14 x 1.2 mm, 0.65 mm pitch,
mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
VFBGA160 15 × 15 x 1 mm, 0.65 mm pitch, mechanical data . . . . . . . . . . . . . . . . . . . . . . 47
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4/52
NANDxxxxNx
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Block diagram for TFBGA107, TFBGA137, and TFBGA149 packages . . . . . . . . . . . . . . . 11
Block diagram for LFBGA137 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Block diagram for TFBGA128, TFBGA152 (NANDA8R3N0, NANDA9R3N0,
NANDBAR3N, NANDB9R3N0), VFBGA152, and VFBGA160 packages . . . . . . . . . . . . . 13
Block diagram for TFBGA152 package (NANDBAR3N0, NANDB0R3N0,
NANDB1R3N0, NANDA0R3N0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
TFBGA107 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
TFBGA128 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
TFBGA137 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
LFBGA137 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
TFBGA149 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
TFBGA152 connections - NANDA8R3N0, NANDA9R3N0, NANDB9R3N0
(top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
TFBGA152 connections - NANDBAR3N0, NANDB0R3N0, NANDB1R3N0,
NANDA0R3N0 (top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
TFBGA152 (NANDBAR3N1) and VFBGA152 (NANDBAR4N5) connections -
(top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
VFBGA160 connections - NANDBAR4N2 (top view through package) . . . . . . . . . . . . . . . 24
Functional block diagram for TFBGA107, TFBGA137, TFBGA149
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Functional block diagram for LFBGA137 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Functional block diagram for TFBGA128 (NANDA9R3N0, NANDB9R3N0),
TFBGA152 (NANDA8R3N0, NANDA9R3N0, NANDBAR3N1,
NANDB9R3N0), VFBGA152 (NANDBAR4N5), and VFBGA160 packages. . . . . . . . . . . . 33
Functional block diagram for TFBGA152 (NANDBAR3N0, NANDB0R3N0,
NANDB1R3N0, NANDA0R3N0) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Functional block diagram for TFBGA128 (NANDBAR3N6) package . . . . . . . . . . . . . . . . . 35
TFBGA107 10.5 × 13 mm - 10 × 14 active ball array, 0.80 mm pitch, package outline . . . 37
TFBGA128 - 2-row perimeter matrix 2R18 × 18, 12 × 12 mm, 0.65 mm pitch,
package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
TFBGA137 10.5 x 13 x 1.2 mm - 10 x 15-13 active ball array, 0.80 mm pitch,
package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
LFBGA137 10.5 x 13 x 1.4 mm - 10 x 15-13 active ball array, 0.80 mm pitch,
package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
TFBGA149 10 × 13.5 mm - 12 × 16 active ball array, 0.80 mm pitch,
package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
TFBGA152, 2-row perimeter matrix 2R21 x 21, 14 x 14 x 1.1 mm, 0.65 mm pitch,
package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
VFBGA152, 2-row perimeter matrix 2R21 x 21, 14 x 14 x 0.9 mm, 0.65 mm pitch,
package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
TFBGA152, 2-row perimeter matrix 2R21 x 21, 14 × 14 x 1.2 mm, 0.65 mm pitch,
package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
VFBGA160 15 × 15 x 1 mm, 0.65 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . 47
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
5/52
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