NB7V58M
1.8 V / 2.5 V / 3.3 V
Differential 2:1 Clock / Data
Multiplexer / Translator
with CML Outputs
Multi−Level Inputs w/ Internal
Termination
Description
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MARKING
DIAGRAM*
16
1
The NB7V58M is a high performance differential 2−to−1 Clock or
Data multiplexer. The differential inputs incorporate internal 50
W
termination resistors that are accessed through the VT pin. This
feature allows the NB7V58M to accept various logic level standards,
such as LVPECL, CML or LVDS.
The NB7V58M produces minimal Clock or Data jitter operating up
to 7 GHz or 10.7 Gb/s, respectively. As such, the NB7V58M is ideal
for SONET, GigE, Fiber Channel, Backplane and other Clock/Data
distribution applications.
The 16 mA differential CML outputs provide matching internal
50
W
terminations and 400 mV output swings when externally
terminated with a 50
W
resistor to V
CC
.
The NB7V58M is offered in a low profile 3 mm x 3 mm 16−pin
QFN package and is a member of the GigaCommt family of high
performance Clock / Data products. For applications that require
equalization, the pin−compatible NB7VQ58M is also available.
Application notes, models, and support documentation are available at
www.onsemi.com.
Features
1
QFN−16
MN SUFFIX
CASE 485G
NB7V
58M
ALYW
G
G
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
SIMPLIFIED BLOCK DIAGRAM
•
•
•
•
•
•
•
•
•
•
•
•
Maximum Input Data Rate > 10.7 Gb/s
Data Dependent Jitter < 10 ps
Maximum Input Clock Frequency > 7 GHz
Random Clock Jitter < 0.8 ps RMS
180 ps Typical Propagation Delay
35 ps Typical Rise and Fall Times
Differential CML Outputs, 400 mV Peak−to−Peak, Typical
Operating Range: V
CC
= 1.71 V to 3.6 V with GND = 0 V
Internal 50
W
Input Termination Resistors
QFN−16 Package, 3 mm x 3 mm
−40°C
to +85°C Ambient Operating Temperature
This is a Pb−Free Device
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
©
Semiconductor Components Industries, LLC, 2009
August, 2009
−
Rev. 0
1
Publication Order Number:
NB7V58M/D
NB7V58M
VT0 GND GND VCC
16
IN0
IN0
IN1
IN1
1
2
NB7V58M
3
4
5
6
7
8
SEL
15
14
13
12 Q
11 GND
10 GND
9
Q
Exposed
Pad (EP)
Multi−Level Inputs
LVPECL, LVDS, CML
IN0
50
W
VT0
50
W
IN0
IN1
50
W
VT1
50
W
IN1
0
2:1
Mux
1
VCC
25 kW
Q
Q
VT1 SEL
NC VCC
Figure 1. Pin Configuration
(Top View)
Figure 2. Detailed Block Diagram
Table 1. SELect FUNCTION TRUTH TABLE
SEL
L
H
Q
IN0
IN1
Q
IN0
IN1
Table 2. PIN DESCRIPTION
Pin
1
2
3
4
5
6
Name
IN0
IN0
IN1
IN1
VT1
SEL
I/O
LVPECL, CML, LVDS Input
LVPECL, CML, LVDS Input
LVPECL, CML, LVDS Input
LVPECL, CML, LVDS Input
−
LVTTL/LVCMOS Input
Description
Noninverted Differential Input (Note 1)
Inverted Differential Input (Note 1)
Noninverted Differential Input (Note 1)
Inverted Differential Input (Note 1)
Internal 50
W
Termination Pin for IN1/IN1
SEL Input. Low for IN0 inputs, high for IN1 inputs. (Note 1) Pin will default HIGH when
left open
(has internal pull−up resistor)
No Connect
−
CML Output
−
−
CML Output
−
−
−
−
−
Positive Supply Voltage (Note 2)
Inverted Differential Output
Negative Supply Voltage
Negative Supply Voltage
Noninverted Differential Output
Positive Supply Voltage (Note 2)
Negative Supply Voltage
Negative Supply Voltage
Internal 50
W
Termination Pin for IN0/IN0
The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the
die for improved heat transfer out of package. The exposed pad must be attached to
a heat−sinking conduit. The pad is electrically connected to the die, and must be elec-
trically and thermally connected to GND on the PC board.
7
8
9
10
11
12
13
14
15
16
−
NC
VCC
Q
GND
GND
Q
VCC
GND
GND
VT0
EP
1. In the differential configuration when the input termination pins (VT0, VT1) are connected to a common termination voltage or left open, and
if no signal is applied on IN0/IN0, IN1/IN1 inputs, then the device will be susceptible to self−oscillation. Q/Q outputs have internal 50
W
source
termination resistors.
2. All VCC and GND pins must be externally connected to a power supply for proper operation.
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NB7V58M
Table 3. ATTRIBUTES
Characteristics
ESD Protection
R
PU
−
SEL Input Pull−up Resistor
Moisture Sensitivity (Note 3)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, see Application Note AND8003/D.
QFN−16
Oxygen Index: 28 to 34
Human Body Model
Machine Model
Value
> 2 kV
> 200 V
25 kW
Level 1
UL 94 V−0 @ 0.125 in
312
Table 4. MAXIMUM RATINGS
Symbol
V
CC
V
IN
V
INPP
I
OUT
I
IN
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
Positive Power Supply
Positive Input Voltage
Differential Input Voltage |INn
−
INn|
Output Current
Input Current Through R
T
(50
W
Resistor)
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient) (Note 4)
Thermal Resistance (Junction−to−Case) (Note 4)
Wave Solder
Pb−Free
0 LFPM
500 LFPM
QFN−16
QFN−16
QFN−16
Continuous
Surge
Condition 1
GND = 0 V
GND = 0 V
Condition 2
Rating
4.0
−0.5
to V
CC
+0.5
1.89
34
40
$40
−40
to +85
−65
to +150
42
35
4
265
Unit
V
V
V
mA
mA
°C
°C
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
4. JEDEC standard multilayer board
−
2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NB7V58M
Table 5. DC CHARACTERISTICS POSITIVE CML OUTPUT
(V
CC
= 1.71 V to 3.6 V; GND = 0 V; T
A
=
−40°C
to 85°C) (Note 5)
Symbol
POWER SUPPLY CURRENT
I
CC
V
OH
Power Supply Current (Inputs and Outputs Open)
100
150
mA
Characteristic
Min
Typ
Max
Unit
CML OUTPUTS
(Note 6)
Output HIGH Voltage
V
CC
= 3.3 V
V
CC
= 2.5 V
V
CC
= 1.8 V
V
CC
= 3.3 V
V
CC
= 2.5 V
V
CC
= 1.8 V
V
CC
– 30
3270
2470
1770
V
CC
– 500
2800
2000
1300
V
CC
– 5
3295
2495
1795
V
CC
– 400
2900
2100
1400
V
CC
3300
2500
1800
V
CC
– 300
3000
2200
1500
mV
V
OL
Output LOW Voltage
mV
DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED
(Note 7) (Figures 6 & 8)
V
th
V
IH
V
IL
V
ISE
V
IHD
V
ILD
V
ID
V
CMR
I
IH
I
IL
V
IH
V
IL
I
IH
I
IL
R
TIN
R
TOUT
Input Threshold Reference Voltage Range (Note 8)
Single−ended Input HIGH Voltage
Single−ended Input LOW Voltage
Single−ended Input Voltage (V
IH
−
V
IL
)
Differential Input HIGH Voltage
Differential Input LOW Voltage
Differential Input Voltage (V
IHD
−
V
ILD
)
Input Common Mode Range (Differential Configuration, Note 10) (Fig-
ure 10)
Input HIGH Current (VTn Open)
Input LOW Current (VTn Open)
1050
V
th
+ 100
GND
200
V
CC
−
100
V
CC
V
th
−
100
1200
mV
mV
mV
mV
DIFFERENTIAL IN0/IN0, IN1/IN1, INPUTS DRIVEN DIFFERENTIALLY
(Figures 6 & 9) (Note 9)
1100
GND
100
1050
−150
−150
V
CC
V
CC
−
100
1200
V
CC
−
50
150
150
mV
mV
mV
mV
mA
mA
CONTROL INPUT
(SEL)
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
V
CC
x 0.65
GND
−150
−200
V
CC
V
CC
x 0.35
+150
+200
mV
mV
mA
mA
TERMINATION RESISTORS
Internal Input Termination Resistor
Internal Output Termination Resistor
45
45
50
50
55
55
W
W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with V
CC
.
6. CML outputs loaded with 50
W
to V
CC
for proper operation.
7. Vth, V
IH
, V
IL
and V
ISE
parameters must be complied with simultaneously.
8. Vth is applied to the complementary input when operating in single−ended mode.
9. V
IHD
, V
ILD,
V
ID
and V
CMR
parameters must be complied with simultaneously.
10. V
CMR
min varies 1:1 with GND, V
CMR
max varies 1:1 with V
CC
. The V
CMR
range is referenced to the most positive side of the
differential input signal.
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NB7V58M
Table 6. AC CHARACTERISTICS
(V
CC
= 1.71 V to 3.6 V; GND = 0 V; T
A
=
−40°C
to 85°C) (Note 11)
Symbol
f
MAX
f
DATAMAX
fSEL
V
OUTPP
t
PLH
,
t
PHL
t
PLH
TC
t
skew
t
DC
t
JITTER
F
N
Maximum Input Clock Frequency
Maximum Operating Data Rate (PRBS23)
Maximum Toggle Frequency, SEL
Output Voltage Amplitude (@ V
INPPmin
)
(Note 12) (Figures 8 & 10)
Propagation Delay to Differential Outputs,
@ 1 GHz, measured at differential cross−point
Propagation Delay Temperature Coefficient
Device
−
Device skew (tpdmax – tpdmin)
Output Clock Duty Cycle
(Reference Duty Cycle = 50%)
RJ – Output Random Jitter (Note 13)
DJ
−
Residual Output Deterministic Jitter (Note 14)
Phase Noise, f
c
= 1 GHz
f
in
v
5.0 GHz
f
in
v
7.0 GHz
f
in
v
7.0 GHz
f
in
v
10.7 Gbps
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
40 MHz
45
40
50
50
0.2
−135
−136
−150
−151
−151
−151
35
0.7
100
Q, Q
15
35
1200
50
f
in
≤
7 GHz
INn/INn to Q, Q
SEL to Q, Q
Characteristic
Voutpp
≥
200 mV
Min
7
10.7
25
200
120
5
Typ
8
12
50
400
180
13
50
50
55
60
0.8
10
240
22
Max
Unit
GHz
Gbps
MHz
mV
ps
ns
Dfs/°C
ps
%
ps RMS
ps pk−pk
dBc
t∫
FN
V
INPP
t
r
, t
f
Integrated Phase Jitter (Figure 4) f
c
= 1 GHz, 12 kHz
−
20 MHz Offset (RMS)
Crosstalk Induced Jitter (Adjacent Channel) (Note 15)
Input Voltage Swing (Differential Configuration) (Figure 10) (Note 16)
Output Rise/Fall Times @ 1 GHz (20%
−
80%)
fs
ps RMS
mV
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured using a V
INPP
min source, 50% duty cycle clock source. All output loading with external 50
W
to V
CC
. Input edge rates 40 ps
(20%
−
80%).
12. Output voltage swing is a single−ended measurement operating in differential mode.
13. Additive RMS jitter with 50% duty cycle clock signal.
14. Additive Peak−to−Peak data dependent jitter with input NRZ data at PRBS23 at 3 Gbps.
15. Crosstalk is measured at the output while applying two similar clock frequencies that are asynchronous with respect to each other at the
inputs.
16. Input voltage swing is a single−ended measurement operating in differential mode.
500
V
OUTPP
, OUTPUT VOLTAGE
AMPLITUDE (mV)
450
POWER (dBc)
0
1
2
3
4
5
6
7
8
9
10
400
350
300
250
200
−115
−120
−125
−130
−135
−140
−145
−150
−155
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
f
in
, CLOCK INPUT FREQUENCY (GHz)
FREQUENCY OFFSET (Hz)
Figure 3. Output Voltage Amplitude (V
OUTPP
) vs. Input
Frequency (f
in
) at Ambient Temperature (Typical)
Figure 4. Typical Phase Noise
(V
CC
= 1.8 V, T = 255C, f
c
= 1 GHz)
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Microchip MCU
