NBSG16
2.5V/3.3V SiGe Differential
Receiver/Driver with
RSECL* Outputs
*Reduced Swing ECL
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The SG16 is a Silicon Germanium differential receiver/driver. The
device is functionally equivalent to the EP16 and LVEP16 devices
with much higher bandwidth and lower EMI capabilities.
Inputs incorporate internal 50
W
termination resistors and accept
NECL (Negative ECL), PECL (Positive ECL), HSTL, GTL, TTL,
CMOS, CML, or LVDS. Outputs are RSECL (Reduced Swing ECL),
400 mV.
The V
BB
and V
MM
pins are internally generated voltage supplies
available to this device only. The V
BB
is used for single–ended NECL
or PECL inputs and the V
MM
pin is used for CMOS inputs. For all
single–ended input conditions, the unused differential input is
connected to V
BB
or V
MM
as a switching reference voltage. V
BB
or
V
MM
may also rebias AC coupled inputs. When used, decouple V
BB
and V
MM
via a 0.01
mF
capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
and V
MM
outputs should be left open.
MARKING
DIAGRAM*
FCBGA–16
BA SUFFIX
CASE 489
SG
16
LYW
L = Wafer Lot
Y = Year
W = Work Week
*For further details, refer to Application Note
AND8002/D
•
•
•
•
Maximum Frequency > 12 GHz Typical
120 ps Typical Propagation Delay
40 ps Typical Rise and Fall Times
RSPECL Output with Operating Range: V
CC
= 2.375 V to 3.465 V
with V
EE
= 0 V
•
RSNECL Output with RSNECL or NECL Inputs with
Operating Range: V
CC
= 0 V with V
EE
= –2.375 V to –3.465 V
•
RSECL Output Level (400 mV Peak–to–Peak Output), Differential
Output Only
•
50
W
Internal Input Termination Resistors
ORDERING INFORMATION
Device
NBSG16BA
NBSG16BAR2
Package
4x4 mm
FCBGA–16
Shipping
810 Units/Tray
4x4 mm
2500/Tape & Reel
FCBGA–16
4x4 mm
FCBGA–16
4x4 mm
FCBGA–16
100 Units/Tray
•
Compatible with Existing 2.5 V/3.3 V LVEP, EP, and LVEL Devices
•
V
BB
and V
MM
Reference Voltage Output
NBSG16BA100
NBSG16BA500R2
500/Tape & Reel
Board
SG16EVB
Description
NBSG16BA Evaluation Board
©
Semiconductor Components Industries, LLC, 2001
1
November, 2001 – Rev. 5
Publication Order Number:
NBSG16/D
NBSG16
1
2
3
4
PIN
A
V
EE
NC
NC
V
EE
D*, D**
Q, Q
B
D
VTD
V
CC
Q
VTD, VTD
V
MM
V
BB
V
CC
V
EE
D
V
EE
V
BB
V
MM
V
EE
NC
PIN DESCRIPTION
FUNCTION
ECL, HSTL, GTL, TTL, CMOS. CML,
LVDS compatible inputs
RSECL Data Outputs
50
W
Internal Input Termination Resistor
CMOS Reference Voltage Output,
(V
CC
–V
EE
)/2
ECL Reference Voltage Output
Positive Supply
Negative Supply
No Connect
C
D
VTD
V
CC
Q
Figure 1. Pinout
(Top View)
NOTE: The NC pins are electrically connected to
the die and MUST be left open or both
pins can be tied to V
CC
.
* Pin will default low when left open.
** Pin will default to a slightly higher potential than D when
both are left open.
V
CC
(B3, C3)
(B2) VTD
50
W
(B1) D
(C1) D
50
W
(C2) VTD
75
KW
36.5
KW
V
MM
(D3)
Q (B4)
Q (C4)
75
KW
V
BB
(D2)
V
EE
(A1, A4, D1, D4)
Figure 2. Logic Diagram
INTERFACING OPTIONS
CML
LVDS
AC–COUPLED
RSECL, PECL, NECL
CONNECTIONS
Connect VTD and VTD to V
CC
Connect VTD and VTD together
Bias VTD and VTD Inputs within (VIHCMR)
Common Mode Range
Standard ECL Termination Techniques
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NBSG16
ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor (D, D)
Internal Input Pullup Resistor (D)
ESD Protection
Moisture Sensitivity (Note 1)
Flammability Rating
Oxygen Index
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Human Body Model
Machine Model
Value
75 kW
36.5 kW
> 2 kV
> 100 V
Level 3
UL 94 V–0 @ 0.125 in
28 to 34
167
MAXIMUM RATINGS
(Note 2)
Symbol
V
CC
V
EE
V
I
I
out
I
BB
I
MM
TA
T
stg
θ
JA
θ
JC
T
sol
Parameter
Positive Power Supply
Negative Power Supply
Positive Input
In ut
Negative Input
Output Current
V
BB
Sink/Source
V
MM
Sink/Source
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction to Ambient)
(Note 3)
Thermal Resistance (Junction to Case)
Wave Solder
0 LFPM
500 LFPM
1S2P (Note 3)
< 15 sec.
16 FCBGA
16 FCBGA
16 FCBGA
Condition 1
V
EE
= 0 V
V
CC
= 0 V
V
EE
= 0 V
V
CC
= 0 V
Continuous
Surge
V
I
V
CC
V
I
V
EE
Condition 2
Rating
3.6
–3.6
3.6
–3.6
25
50
1
1
–40 to +85
–65 to +150
108
86
5
225
Units
V
V
V
V
mA
mA
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C
2. Maximum Ratings are those values beyond which device damage may occur.
3. JEDEC standard multilayer board – 1S2P (1 signal, 2 power)
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NBSG16
DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT
V
CC
= 2.5 V; V
EE
= 0 V (Note 4)
–40°C
Symbol
I
EE
V
OH
V
PP
V
IH
V
IL
V
BB
V
IHCMR
V
MM
R
T
I
IH
I
IL
Characteristic
Power Supply Current
Output HIGH Voltage (Note 5)
Output P–P Voltage
Input HIGH Voltage
(Single Ended) (Note 6)
Input LOW Voltage
(Single Ended) (Note 6)
PECL Output Voltage Reference
Input HIGH Voltage Common
Mode Range (Note 7)
CMOS Output Voltage Reference
V
CC
/2
Internal Termination Resistor
Input HIGH Current (@ V
IH
)
Input LOW Current (@ V
IL
)
Min
17
1450
350
V
THR
+
75 mV
V
EE
1080
1.2
1200
45
1250
50
30
25
Typ
23
1530
410
V
CC
–
1.0*
V
CC
–
1.4*
1140
Max
29
1575
525
V
CC
V
THR
–
75 mV
1200
2.5
1400
55
100
50
Min
17
1525
350
V
THR
+
75 mV
V
EE
1080
1.2
1200
45
1250
50
30
25
25°C
Typ
23
1565
410
V
CC
–
1.0*
V
CC
–
1.4*
1140
Max
29
1600
525
V
CC
V
THR
–
75 mV
1200
2.5
1400
55
100
50
Min
17
1550
350
V
THR
+
75 mV
V
EE
1080
1.2
1200
45
1250
50
30
25
85°C
Typ
23
1590
410
V
CC
–
1.0*
V
CC
–
1.4*
1140
Max
29
1625
525
V
CC
V
THR
–
75 mV
1200
2.5
1400
55
100
50
Unit
mA
mV
mV
V
V
mV
V
mV
Ω
µA
µA
NOTE: SiGe circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
4. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.125 V to –0.965 V.
5. All loading with 50 ohms to V
CC
–2.0 volts.
6. V
THR
is the voltage applied to the complementary input, typically V
BB
or V
MM
.
7. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
*Typicals used for testing purposes.
DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT
V
CC
= 3.3 V; V
EE
= 0 V (Note 8)
–40°C
Symbol
I
EE
V
OH
V
PP
V
IH
V
IL
V
BB
V
IHCMR
V
MM
R
T
I
IH
I
IL
Characteristic
Power Supply Current
Output HIGH Voltage (Note 9)
Output P–P Voltage
Input HIGH Voltage
(Single Ended) (Note 10)
Input LOW Voltage
(Single Ended) (Note 10)
PECL Output Voltage Reference
Input HIGH Voltage Common
Mode Range (Note 11)
CMOS Output Voltage Reference
V
CC
/2
Internal Termination Resistor
Input HIGH Current (@ V
IH
)
Input LOW Current (@ V
IL
)
Min
17
2250
350
V
THR
+
75 mV
V
EE
1880
1.2
1600
45
1650
50
30
25
Typ
23
2330
410
V
CC
–
1.0*
V
CC
–
1.4*
1940
Max
29
2375
525
V
CC
V
THR
–
75 mV
2000
3.3
1800
55
100
50
Min
17
2325
350
V
THR
+
75 mV
V
EE
1880
1.2
1600
45
1650
50
30
25
25°C
Typ
23
2365
410
V
CC
–
1.0*
V
CC
–
1.4*
1940
Max
29
2400
525
V
CC
V
THR
–
75 mV
2000
3.3
1800
55
100
50
Min
17
2350
350
V
THR
+
75 mV
V
EE
1880
1.2
1600
45
1650
50
30
25
85°C
Typ
23
2390
410
V
CC
–
1.0*
V
CC
–
1.4*
1940
Max
29
2425
525
V
CC
V
THR
–
75 mV
2000
3.3
1800
55
100
50
Unit
mA
mV
mV
V
V
mV
V
mV
Ω
µA
µA
NOTE: SiGe Circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
8. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary +0.925 V to –0.165 V.
9. All loading with 50 ohms to V
CC
–2.0 volts.
10. V
THR
is the voltage applied to the complementary input, typically V
BB
or V
MM
.
11. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
*Typicals used for testing purposes.
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NBSG16
DC CHARACTERISTICS, NECL OR RSNECL INPUT WITH NECL OUTPUT
V
CC
= 0 V; V
EE
= –3.465 V to –2.375 V (Note 12)
–40°C
Symbol
I
EE
V
OH
V
PP
V
IH
V
IL
V
BB
V
IHCMR
Characteristic
Power Supply Current
Output HIGH Voltage (Note 13)
Output P–P Voltage
Input HIGH Voltage
(Single Ended) (Note 14)
Input LOW Voltage
(Single Ended) (Note 14)
NECL Output Voltage Reference
Input HIGH Voltage Common
Mode Range (Differential)
(Note 15)
CMOS Output Voltage Reference
(Note 16)
Input HIGH Current (@ V
IH
)
Input LOW Current (@ V
IL
)
Min
17
–1050
350
V
THR
+
75 mV
V
EE
–1420
Typ
23
–970
410
V
CC
–
1.0*
V
CC
–
1.4*
–1360
Max
29
–925
525
V
CC
V
THR
–
75 mV
–1300
0.0
Min
17
–975
350
V
THR
+
75 mV
V
EE
–1420
25°C
Typ
23
–935
410
V
CC
–
1.0*
V
CC
–
1.4*
–1360
Max
29
–900
525
V
CC
V
THR
–
75 mV
–1300
0.0
Min
17
–950
350
V
THR
+
75 mV
V
EE
–1420
85°C
Typ
23
–910
410
V
CC
–
1.0*
V
CC
–
1.4*
–1360
Max
29
–875
525
V
CC
V
THR
–
75 mV
–1300
0.0
Unit
mA
mV
mV
V
V
mV
V
V
EE
+1.2
V
EE
+1.2
V
EE
+1.2
V
MM
I
IH
I
IL
V
MMT
–
50
V
MMT
30
25
V
MMT
+ 150
100
50
V
MMT
–
50
V
MMT
30
25
V
MMT
+ 150
100
50
V
MMT
–
50
V
MMT
30
25
V
MMT
+ 150
100
50
mV
µA
µA
NOTE: SiGe circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
12. Input and output parameters vary 1:1 with V
CC
.
13. All loading with 50 ohms to V
CC
–2.0 volts.
14. V
THR
is the voltage applied to the complementary input, typically V
BB
or V
MM
.
15. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
16. V
MM
typical = |V
CC
– V
EE
|/2 + V
EE
= V
MMT
*Typicals used for testing purposes.
AC CHARACTERISTICS
V
CC
= 0 V; V
EE
= –3.465 V to –2.375 V or V
CC
= 2.375 V to 3.465 V; V
EE
= 0 V
–40°C
Symbol
f
max
t
PLH
,
t
PHL
t
SKEW
t
JITTER
V
INPP
t
r
t
f
Characteristic
Maximum Frequency
(See Figure 3. F
max
/JITTER) (Note 17)
Propagation Delay to
Output Differential
Duty Cycle Skew (Note 18)
Cycle–to–Cycle Jitter (RMS)
(See Figure 3. F
max
/JITTER) (Note 17)
Input Voltage Swing/Sensitivity
(Differential) (Note 19)
Output Rise/Fall Times
(20% – 80%)
Q, Q
75
30
45
Min
10.709
90
Typ
> 12
110
3
0.3
130
15
<1
2600
75
75
20
40
Max
Min
10.709
100
25°C
Typ
> 12
120
3
0.3
140
15
<1
2600
65
75
20
40
Max
Min
10.709
105
85°C
Typ
> 12
125
3
0.3
145
15
<1
2600
65
Max
Unit
GHz
ps
ps
ps
mV
ps
17. Measured using a 400 mV source, 50% duty cycle clock source. All loading with 50 ohms to V
CC
–2.0 V.
18. See Figure 5. t
skew
= |t
PLH
– t
PHL
| for a nominal 50% differential clock input waveform.
19. V
INPP(max)
cannot exceed V
CC
– V
EE
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