NC7SV57 / NC7SV58 — TinyLogic
®
ULP-A Universal Configuration Two-Input Logic Gates
December 2010
NC7SV57 / NC7SV58
TinyLogic
®
ULP-A Universal Configurable Two-Input
Logic Gates
Features
0.9V to 3.6V V
CC
Supply Operation
3.6V Over-Voltage Tolerant I/Os at V
CC
from 0.9V to 3.6V
Extremely High Speed t
PD
- 2.5ns: Typical for 2.7V to 3.6V V
CC
- 3.1ns: Typical for 2.3V to 2.7V V
CC
- 4.0ns: Typical for 1.65V to 1.95V V
CC
- 6.0ns: Typical for 1.4V to 1.6V V
CC
- 8.0ns: Typical for 1.1V to 1.3V V
CC
- 23.0ns: Typical for 0.9V V
CC
Power-Off High-Impedance Inputs and Outputs
High Static Drive (I
OH
/I
OL
)
-
±24mA
at 3.00V V
CC
-
±18mA
at 2.30V V
CC
-
±6mA
at 1.65V V
CC
-
±4mA
at 1.4V V
CC
-
±2mA
at 1.1V V
CC
-
±0.1mA
at 0.9V V
CC
Proprietary Quiet Series™ Noise/EMI Reduction
Ultra-Small MicroPak™ Package
Ultra-Low Dynamic Power
Description
The NC7SV57 and NC7SV58 are universal configurable
two-input logic gates from Fairchild’s Ultra-Low Power
®
(ULP-A) series of TinyLogic . ULP-A is ideal for
applications that require extreme high-speed, high
drive, and low power. This product is designed for a
wide low-voltage operating range (0.9V to 3.6V V
CC
)
and applications that require more drive and speed than
®
the TinyLogic ULP series, but still offer best-in-class,
low-power operation.
Each device is capable of being configured for 1 of 5
unique two-input logic functions. Any possible two-input
combinatorial logic function can be implemented, as
shown in the
Function Selection Table.
Device
functionality is selected by how the device is wired at
the board level.
Figures 1 through 10
illustrate how to
connect the NC7SV57 and NC7SV58, respectively, for
the desired logic function. All inputs have been
implemented with hysteresis.
The NC7SV57 and NC7SV58 are uniquely designed for
optimized power and speed and are fabricated with an
advanced CMOS technology to achieve high-speed
operation while maintaining low CMOS power
dissipation.
Ordering Information
Part Number
NC7SV57P6X
NC7SV57L6X
NC7SV57FHX
NC7SV58P6X
NC7SV58L6X
NC7SV58FHX
Top Mark
V57
H3
H3
V58
H4
H4
Package
6-Lead SC70, EIAJ SC-88a, 1.25mm Wide
6-Lead Micropak™, 1.0mm Wide
6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch
6-Lead SC70, EIAJ SC-88a, 1.25mm Wide
6-Lead Micropak™, 1.0mm Wide
6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch
Packing Method
3000 Units on
Tape & Reel
5000 Units on
Tape & Reel
3000 Units on
Tape & Reel
5000 Units on
Tape & Reel
© 2002 Fairchild Semiconductor Corporation
NC7SV57 • NC7SV58 • Rev. 1.0.4
www.fairchildsemi.com
NC7SV57 / NC7V58 — TinyLogic
®
ULP A Universal Configuration Two-Input Logic Gates
Battery Life
Figure 1. Battery Life vs. V
CC
Supply Voltage
Notes:
®
1. TinyLogic ULP and ULP-A with up to 50% less power consumption can extend your battery life significantly.
Battery Life
=
(V
battery
•I
battery
•.9)/(P
device
)/24hrs/day
2
where P
device
=
(I
CC
• V
CC
)
+
(C
PD
+
C
L
) • V
CC
• f.
2. Assumes ideal 3.6V Lithium Ion battery with current rating of 900mAH and derated 90% and device frequency at
10MHz, with C
L
= 15pF load.
© 2002 Fairchild Semiconductor Corporation
NC7SV57 • NC7SV58 • Rev. 1.0.4
www.fairchildsemi.com
2
NC7SV57 / NC7V58 — TinyLogic
®
ULP A Universal Configuration Two-Input Logic Gates
Pin Configurations
Figure 2. SC70 (Top View)
Figure 3. MicroPak™ (Top Through View)
Figure 4. Pin 1 Orientation
Notes:
3. AAA represents product code top mark (see
Ordering Information).
4. Orientation of top mark determines pin one location.
5. Reading the top mark left to right, pin one is the lower left pin.
Pin Definitions
Pin # SC70
1
2
3
4
5
6
Pin # MicroPak™
1
2
3
4
5
6
Name
I
1
GND
I
0
Y
V
CC
I
2
Description
Data Input
Ground
Data Input
Output
Supply Voltage
Data Input
© 2002 Fairchild Semiconductor Corporation
NC7SV57 • NC7SV58 • Rev. 1.0.4
www.fairchildsemi.com
3
NC7SV57 / NC7V58 — TinyLogic
®
ULP A Universal Configuration Two-Input Logic Gates
Function Table
Inputs
I
2
L
L
L
L
H
H
H
H
NC7SV57
I
0
L
H
L
H
L
H
L
H
NC7SV58
Y = (I
0
) • (I
2
) + (I
1
) • (I
2
)
L
H
L
H
H
H
L
L
I
1
L
L
H
H
L
L
H
H
Y = (I
0
) • (I
2
) + (I
1
) • (I
2
)
H
L
H
L
L
L
H
H
H = HIGH Logic Level
L = LOW Logic Level
Function Selection Table
2-Input Logic Function
2-Input AND
2-Input AND with Inverted Input
2-Input AND with Both Inputs Inverted
2-Input NAND
2-Input NAND with Inverted Input
2-Input NAND with Both Inputs Inverted
2-Input OR
2-Input OR with Inverted Input
2-Input OR with Both Inputs Inverted
2-Input NOR
2-Input NOR with Inverted Input
2-Input NOR with Both Inputs Inverted
2-Input XOR
2-Input XNOR
Device Selection
NC7SV57
NC7SV58
NC7SV57
NC7SV58
NC7SV57
NC7SV58
NC7SV58
NC7SV57
NC7SV58
NC7SV57
NC7SV58
NC7SV57
NC7SV58
NC7SV57
Connection Configuration
Figure 5
Figure 11, Figure 12
Figure 8
Figure 10
Figure 6, Figure 7
Figure 13
Figure 13
Figure 6, Figure 7
Figure 10
Figure 8
Figure 10, Figure 11
Figure 5
Figure 14
Figure 9
© 2002 Fairchild Semiconductor Corporation
NC7SV57 • NC7SV58 • Rev. 1.0.4
www.fairchildsemi.com
4
NC7SV57 / NC7V58 — TinyLogic
®
ULP A Universal Configuration Two-Input Logic Gates
NC7SV57 Logic Configurations
Figure 5
that can
diagrams
for a
through Figure 9 show the logical functions
be implemented using the NC7SV57. The
show the DeMorgan’s equivalent logic duals
given two-input function. The logical
implementation is next to the board-level physical
implementation of how the pins of the function should
be connected.
Figure 5.
2-Input AND Gate
Figure 6.
2-Input NAND Gate with Inverted A Input
Figure 7.
2-Input NAND with Inverted B Input
Figure 8.
2-Input NOR Gate
Figure 9.
2-Input XNOR Gate
© 2002 Fairchild Semiconductor Corporation
NC7SV57 • NC7SV58 • Rev. 1.0.4
www.fairchildsemi.com
5
