NCN6024
Compact and Low Cost
Smart Card Interface IC
The NCN6024 is a compact and low cost single smart card interface
IC. It is dedicated for 3.0 V/5.0 V smart card reader/writer
applications.
The device is fully compatible with the ISO 7816−3 and EMV
standards as well as with standards specifying conditional access in
Set−Top−Box (STB).
Features
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MARKING
DIAGRAMS
28
NCN6024
AWLYYWWG
SOIC−28*
CASE 751F
1
•
Single IC Card Interface
•
Fully Compatible with ISO 7816−3, EMV and Related Standards
•
•
•
•
•
•
•
•
•
•
•
•
Including STB Standards
Three Protected Bidirectional Buffered I/O Lines (C4, C7 and C8
Card Pins)
3.0 V or 5.0 V
±
5% Regulated Card Power Supply such as ICC
≤
65 mA at VDDP = 4.5 V to 5.5 V
Independent Power Supply on Controller Interface
(2.7 V < V
DD
< 5.5 V)
Thermal and Short Circuit Protection on all Card Pins
Support up to 20 MHz Clock with Internal Division Ratio 1/1, 1/2,
1/4 and 1/8 through CLKDIV1 and CLKDIV2
ESD Protection on Card Pins up to 8 kV+ (Human Body Model)
Activation/Deactivation Sequences
Fault Protection Mechanisms Enabling Automatic Device
Deactivation in Case of Overload, Overheating, Card Take−off or
Power Supply Drop−out
Interrupt Signal INT for Card Presence and Faults
External Undervoltage Lockout Threshold Adjustment on V
DD
(PORADJ Pin)
Available in 2 Package Formats: SOIC−28 and TSSOP−28
These are Pb−Free Devices
*Consult Sales Office
NCN
6024G
ALYW
TSSOP−28
CASE 948AA
NCN6024 = Specific Device Code
A
= Assembly Location
WL, L = Wafer Lot
YY, Y
= Year
WW, W = Work Week
G
= Pb−Free Package
Typical Application
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
•
Pay TV, Set Top Box Decoder with Conditional Access and
•
•
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Pay−per−View
Conditional Access Module (CAM)
Portable Systems
Point Of Sales and Transaction Terminals
Electronic Payment and Identification
©
Semiconductor Components Industries, LLC, 2009
July, 2009
−
Rev. 1
1
Publication Order Number:
NCN6024/D
NCN6024
VDDP
10 uF
VDD
100 nF
Microcontroller
VDD
R1
R2
NCN6024
CMDVCC
5V/3V
CLKDIV1
CLKDIV2
CLK_IN
VDD
INT
PORADJ
100 nF
VDDP
C1
C2
VUP
CRD_PRES
CRD_PRES
CRD_VCC
CRD_RST
CRD_CLK
CRD_AUX1
CRD_AUX2
CRD_IO
CRD_GND
GNDP
GND
GND
GND
100 nF
GND
220 nF
1
2
3
4
100 nF
100 nF
SMART CARD
DET
Vcc
RST
CLK
C4
DET
GND
Vpp
I/O
C8
CONTROL
5 GND
6
7
8
DATAPORT
RSTIN
I/Ouc
AUX1uc
AUX2uc
Figure 1. Typical Smart Card Interface Application
CLKDIV1
CLKDIV2
5V/3V
GNDP
C2
VDDP
C1
VUP
CRD_PRES
CRD_PRES
CRD_I/O
CRD_AUX2
CRD_AUX1
CRD_GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AUX2uc
AUX1uc
I/Ouc
NC
CLKIN
INT
GND
VDD
RSTIN
CMDVCC
PORADJ
CRD_VCC
CRD_RST
CRD_CLK
Figure 2. SOIC−28 and TSS0P−28 Pinout (Top View)
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2
NCN6024
VDD
21
VDDP
6
9 CRD_PRES
INT
23
Interrupt Block
Card Detection
10 CRD_PRES
5V/3V
CMDVCC
PORADJ
CLKDIV1
CLKDIV2
3
19
18
1
2
Thermal Control
Clock Dividers
Supply Voltage
Monitoring
DC/DC Converter
Internal Oscillator 2.5 MHz
17 CRD_VCC
4
8
GNDP
VUP
5
7
C2
C1
CLKIN
NC
RSTIN
I/Ouc
AUX2uc
24
25
20
26
27
28
22
15 CRD_CLK
Control Logic
and Sequencer
Card Pin
Drivers
16 CRD_RST
11 CRD_I/O
13 CRD_AUX2
12 CRD_AUX1
14 CRD_GND
AUX1uc
GND
Figure 3. NCN6024 Block Diagram
PIN FUNCTION AND DESCRIPTION
Pin #
1
2
3
4
5
6
7
8
9
10
Name
CLKDIV1
CLKDIV2
5V/3V
GNDP
C2
VDDP
C1
VUP
CRD_PRES
CRD_PRES
Type
Input
Input
Input
GND
Power
Power
Power
Power
Input
Input
Description
This pin coupled with CLKDIV2 is used to program the clock frequency division ratio (Table 1).
This pin coupled with CLKDIV1 is used to program the clock frequency division ratio (Table 1).
Allows selecting card V
CC
power supply voltage. CRD_VCC = 5 V when 5V/3V = HIGH or 3 V when
5V/3V = LOW
DC/DC Converter Power Supply Ground
DC/DC Converter Capacitor pin number 2
−
A 100 nF capacitor is connected between this pin and
pin C1. The capacitor has to feature an ESR lower than 100 mW
DC/DC Converter Power Supply Voltage
DC/DC Converter Capacitor pin number 1
−
A 100 nF capacitor is connected between this pin and
pin C2. The capacitor has to feature an ESR lower than 100 mW
Charge−pump output tank capacitor
−
a very low ESR 100 nF capacitor (ESR< 100 mW) is
connected between this pin and GNDP
Card presence pin active (card present) when CRD_PRES = Low. A built−in debounce timer of
about 8 ms is activated when a card is inserted.
Card presence pin active (card present) when CRD_PRES = High. A built−in debounce timer of
about 8 ms is activated when a card is inserted.
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NCN6024
PIN FUNCTION AND DESCRIPTION
Pin #
11
Name
CRD_I/O
Type
Input/
Output
Input/
Output
Input/
Output
GND
Output
Output
Power
Description
This pin handles the connection to the serial I/O (C7) of the card connector. A bi−directional level
translator adapts the serial I/O signal between the card and the micro controller. A 13 kW (typical)
pullup resistor to CRD_VCC provides a High impedance state for the smart card I/O link.
This pin handles the connection to the chip card’s serial auxiliary AUX2 I/O pin (C8). A bi−directional
level translator adapts the serial I/O signal between the card and the micro controller. A 13 kW
(typical) pullup resistor to CRD_VCC provides a High impedance state for the smart card C8 pin.
This pin handles the connection to the chip card’s serial auxiliary AUX1 I/O pin (C4). A bi−directional
level translator adapts the serial I/O signal between the card and the micro controller. An 13 kW
(typical) pullup resistor to CRD_VCC provides a High impedance state for the smart card C4 pin.
Card Ground
This pin is connected to the CLOCK card connector’s pin (Chip card’s pin C3). The Clock signal
comes from the CLKIN input through clock dividers and level shifter.
This pin is connected to the chip card’s RESET pin (C2) through the card connector. A level
translator adapts the external Reset (RSTIN) signal to the smart card.
This pin is connected to the smart card power supply pin. An internal DC/DC converter is
programmable using the pin 5V/3V to supply either 5 V or 3 V output voltage. An external distributed
ceramic capacitor ranging from 320 nF to 500 nF recommended must be connected across
CRD_VCC and CRD_GND. This set of capacitor (if distributed) must be low ESR (< 100 mW).
Power−on reset threshold adjustment input pin for changing the reset threshold due to an external
resistor power divider. Needs to be connected to ground when unused.
Command VCC pin. Activation sequence Enable/Disable pin (active Low). The activation sequence is
enabled by toggling CMDVCC High to Low and when a card is present.
This Reset input connected to the host and referred to V
DD
(microcontroller side), is connected to
the smart card Reset pin through the internal level shifter which translates the level according to the
CRD_VCC programmed value.
This pin is connected to the system controller power supply. It configures the level shifter input
stage to accept the signals coming from the controller. A 0.1
mF
capacitor shall be used to bypass
the power supply voltage. When V
DD
is below 2.35 V typical the card pins are disabled.
Ground
The interrupt request is activated LOW on this pin. This is enabled when a card is present and the
card presence is detected by CRD_PRES or CRD_PRES pins. Similarly an interrupt is generated
when CRD_VCC is overloaded. 20 kW typical integrated pullup resistor to V
DD
.
Clock Input for External Clock
Unconnected
Input/
Output
Input/
Output
Input/
Output
This pin is connected to an external micro−controller. A bi−directional level translator adapts the
serial I/O signal between the smart card and the external controller. A built−in constant 13 kW
(typical) resistor provides a high impedance state.
This pin is connected to an external micro−controller. A bi−directional level translator adapts the
serial C4 signal between the smart card and the external controller. A built−in constant 13 kW
(typical) resistor provides a high impedance state.
This pin is connected to an external micro−controller. A bi−directional level translator adapts the
serial C8 signal between the smart card and the external controller. A built−in constant 13 kW
(typical) resistor provides a high impedance state.
12
CRD_AUX2
13
CRD_AUX1
14
15
16
17
CRD_GND
CRD_CLK
CRD_RST
CRD_VCC
18
19
20
PORADJ
CMDVCC
RSTIN
Input
Input
Input
21
VDD
Power
22
23
GND
INT
GND
Output
24
25
26
CLKIN
NC
I/Ouc
Input
27
AUX1uc
28
AUX2uc
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4
NCN6024
ATTRIBUTES
Characteristics
ESD protection
Human Body Model (HBM) (Note 1)
Card Pins (Card Interface Pins 9
−
17)
All Other Pins
Machine Model (MM)
Card Pins (Card Interface Pins 9
−
17)
All Other Pins
Moisture sensitivity (Note 2) SOIC−28 and TSSOP−28
Flammability Rating Oxygen
Index: 28 to 34
Values
8 kV
2 kV
400 V
150 V
Level 1
UL 94 V−0 @ 0.125 in
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latch−up Test
1. Human Body Model (HBM), R = 1500
W,
C = 100 pF.
2. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS
(Note 3)
Rating
DC/DC Converter Power Supply Voltage
Power Supply from Microcontroller Side
External Card Power Supply
Charge Pump Output
Digital Input Pins
Digital Output Pins (I/Ouc, AUX1uc, AUX2uc, INT)
Smart Card Output Pins
Thermal Resistance Junction−to−Air
Operating Ambient Temperature Range
Operating Junction Temperature Range
Maximum Junction Temperature
Storage Temperature Range
SOIC−28
TSSOP−28
Symbol
V
DDP
V
DD
CRD_VCC
V
UP
V
in
V
out
V
out
R
qJA
T
A
T
J
T
Jmax
T
stg
Value
−0.3
v
VDDP
v
5.5
−0.3
v
VDD
v
5.5
−0.3
v
CRD_VCC
v
5.5
−0.3
v
V
UP
v
5.5
−0.3
v
V
in
v
V
DD
−0.3
v
V
out
v
V
DD
−0.3
v
V
out
v
CRD_V
CC
75
76
−40
to +85
−40
to +125
+125
−65
to + 150
V
V
V
°C/W
°C
°C
°C
°C
Unit
V
V
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at T
A
= +25°C
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