NCP1124, NCP1126,
NCP1129
High Voltage Switcher for
Offline Power Supplies
The NCP112x products integrates a fixed−frequency peak current
mode controller with a low on−resistance, 650 V MOSFET. Available
in a PDIP−7 package, the NCP112x offers a high level of integration,
including soft−start, frequency−jittering, short−circuit protection,
thermal shutdown protection, frequency foldback mode and
skip−cycle to reduce power consumption in light load condition, peak
current mode control with adjustable internal ramp compensation and
adjustable peak current set point.
During nominal load operation, the part switches at one of the
available frequencies (65 or 100 kHz). When the output power
demand diminishes, the IC automatically enters frequency foldback
mode and provides excellent efficiency at light loads. When the power
demand reduces further, it enters into a skip mode to reduce the
standby consumption down to no load condition.
Protection features include: a timer to detect an overload or a
short−circuit event with auto−recovery or latch protection, and a
built−in V
CC
overvoltage protection.
The switcher also provides a jittered 65 kHz or 100 kHz switching
frequency to improve the EMI.
Features
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PDIP−7
P SUFFIX
CASE 626B
MARKING DIAGRAMS
112xyPzzz
AWL
YYWWG
1
x
= Specific Device Code
4 = NCP1124
6 = NCP1126
9 = NCP1129
= A or B
A = Latch
B = Auto−recovery
= Frequency
65 = 65 kHz
100 = 100 kHz
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
y
•
•
•
•
•
•
•
•
•
•
•
Built−in 650 V, 1 A MOSFET with R
DS(on)
of 8.6
W
for NCP1124
Built−in 650 V, 1.8 A MOSFET with R
DS(on)
of 5.4
W
for NCP1126
Built−in 650 V, 5.5 A MOSFET with R
DS(on)
of 2.1
W
for NCP1129
Fixed−Frequency 65 or 100 kHz Current Mode Control with
Adjustable Internal Ramp Compensation
Adjustable Current Limit with External Resistor
Frequency Foldback Down to 26 kHz and Skip−Cycle for Light Load
Efficiency
Frequency Jittering for EMI Improvement
Less than 100 mW Standby Power @ High Line
EPS 2.0 Compliant
7−Pin Package Provides Creepage Distance
These are Pb−Free Devices
zzz
A
WL
YY
WW
G
ORDERING INFORMATION
See detailed ordering and shipping information on page 17 of
this data sheet.
Table 1. OUTPUT POWER TABLE
(Note 1)
230 Vac
+
15%
(Note 4)
Product
NCP1124
NCP1126
NCP1129
1.
2.
3.
4.
Adapter
(Note 2)
12 W
15 W
28 W
Peak or Open Frame
(Note 3)
27 W
32 W
43 W
Adapter
(Note 2)
6W
10 W
20 W
85 − 265 Vac
Peak or Open Frame
(Note 3)
14 W
17 W
26.5 W
12 V output voltage with 135 V reflected output voltage
Typical continuous power in a non-ventilated enclosed adaptor measured at 50°C ambient temperature.
Maximum practical continuous power in an open-frame design at 50°C ambient temperature
230 V
AC
or 115 V
AC
with voltage doubler.
©
Semiconductor Components Industries, LLC, 2015
1
March, 2015 − Rev. 3
Publication Order Number:
NCP1126/D
NCP1124, NCP1126, NCP1129
Figure 1. Typical Application
Table 2. PIN FUNCTION DESCRIPTION
Pin No.
1
2
3
4
5
6
7
8
Pin Name
VCC
FB
CS
Source
Drain
Drain
−
GND
Pin Description
This pin is connected to an external auxiliary voltage and supplies the controller. When above a certain
level, the part fully latches off.
Feedback input. Hooking an optocoupler collector to this pin will allow regulation.
This pin monitors the primary peak current but also offers a means to introduce ramp compensation.
Source of the internal MOSFET. This pin is typically connected to the source of a grounded sense resistor.
The drain of the internal MOSFET. These pins connect to the transformer terminal and can withstand up to
650 V.
Removed for creepage distance.
Ground reference.
Table 3. OPTIONS
Switcher
NCP1124AP65G
NCP1124BP65G
NCP1124AP100G
NCP1124BP100G
NCP1126AP65G
NCP1126BP65G
NCP1126AP100G
NCP1126BP100G
NCP1129AP65G
NCP1129BP65G
NCP1129AP100G
NCP1129BP100G
Package
PDIP−7
PDIP−7
PDIP−7
PDIP−7
PDIP−7
PDIP−7
PDIP−7
PDIP−7
PDIP−7
PDIP−7
PDIP−7
PDIP−7
Frequency
65 kHz
65 kHz
100 kHz
100 kHz
65 kHz
65 kHz
100 kHz
100 kHz
65 kHz
65 kHz
100 kHz
100 kHz
Short−Circuit Protection
Latch
Auto−Recovery
Latch
Auto−Recovery
Latch
Auto−Recovery
Latch
Auto−Recovery
Latch
Auto−Recovery
Latch
Auto−Recovery
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2
NCP1124, NCP1126, NCP1129
V
CC
and logic
management
double hiccup
I
pflag
Power
On Reset
S Q
Q
R
V
DD
Power
on reset
4 kW
R
LIM
V
OVP
+
−
Clamp
Drain
U
VLO
V
DD
Vcc
−
+
Source
Frequency
Modulation
+
−
65/100 kHz
clock
S
Q
Q
Frequency
foldback
V
fold
Slope
Compensation
R
− +
−
V
ILIM
I
pflag
4 ms 5 s
250 mV Peak
Current Freeze
+
R
ramp
The soft start is activated
− startup process
− auto recovery
GND
LEB
+
− V
skip
+
+
VDD
−
R
FB
FB
/4
CS
Figure 2. Functional Block Diagram
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3
NCP1124, NCP1126, NCP1129
Table 4. MAXIMUM RATINGS
(Note 5)
Rating
Drain Input Voltage (Referenced to Source Terminal)
Drain Maximum Pulsed Current
(10
ms
Single Pulse, T
J
= 25°C)
Single Pulse Avalanche Energy
Supply Input Voltage
Current Sense Input Voltage
Feedback Input Voltage
Operating Junction Temperature
Storage Temperature Range
Power Dissipation (T
A
= 25_C, 2 Oz Cu, 600 mm
2
Printed Circuit Copper Clad)
Thermal Resistance, Junction to Ambient 2 Oz Cu Printed Circuit Copper Clad
Low Conductivity (Note 6)
High Conductivity (Note 7)
ESD Capability (Note 8)
Human Body Model ESD Capability per JEDEC JESD22−A114F.
Machine Model ESD Capability per JEDEC JESD22−A115C.
Charged−Device Model ESD Capability per JEDEC JESD22−C101E.
NCP112x
NCP1129
NCP1126
NCP1124
NCP1126, NCP1129
NCP1124
Symbol
V
Drain
I
DM
Value
−0.3 to 650
27
11
7
96
60
−0.3 to 35
−0.3 to 10
−0.3 to 10
−40 to 150
–60 to 150
1.5
128
78
V
2000
200
500
Unit
V
A
E
AS
V
CC(MAX)
V
CS
V
FB
T
J
T
STG
P
D
R
θJA
mJ
V
V
V
_C
_C
W
_C/W
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
5. This device contains Latch−Up protection and exceeds
±100
mA per JEDEC Standard JESD78.
6. Low Conductivity Board. As mounted on 40 x 40 x 1.5 mm FR4 substrate with a single layer of 50 mm
2
of 2 oz copper trances and heat
spreading area. As specified for a JEDEC 51 low conductivity test PCB. Test conditions were under natural convection of zero air flow.
7. High Conductivity Board. As mounted on 40 x 40 x 1.5 mm FR4 substrate with a single layer of 600 mm
2
of 2 oz copper trances and heat
spreading area. As specified for a JEDEC 51 high conductivity test PCB. Test conditions were under natural convection of zero air flow.
8. The Drain pins (5 and 6), are rated to the maximum voltage of the device, or 650 V.
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4
NCP1124, NCP1126, NCP1129
Table 5. ELECTRICAL CHARACTERISTICS
(V
CC
= 12 V, for typical values T
J
= 25_C, for min/max values, T
J
is –40_C to 125_C, unless otherwise noted)
Characteristics
STARTUP AND SUPPLY CIRCUITS
Supply Voltage
Startup Threshold
Minimum Operating Voltage
Operating Hysteresis
V
CC
Overvoltage Protection Threshold
V
CC
Overvoltage Protection Filter Delay
V
CC
Clamp Voltage in Latch Mode
Supply Current
Startup Current
Skip Current
Operating Current at 65 kHz
Operating Current at 100 kHz
Current Consumption in Latch Mode
POWER SWITCH CIRCUIT
Off−State Leakage Current
Breakdown Voltage
ON State Resistance
NCP1129
NCP1126
NCP1124
Output Capacitance
NCP1129
NCP1126
NCP1124
Rise Time
Fall Time
Rise Time
Fall Time
Rise Time
Fall Time
T
J
= 125_C, V
Drain
= 650 V
T
J
= 25_C, I
Drain
= 250
mA,
V
FB
= 0 V
I
Drain
= 100 mA
V
CC
= 10 V, T
J
= 25_C
V
CC
= 10 V, T
J
= 125_C
V
CC
= 10 V, T
J
= 25_C
V
CC
= 10 V, T
J
= 125_C
V
CC
= 10 V, T
J
= 25_C
V
CC
= 10 V, T
J
= 125_C
V
DS
= 25 V, V
CC
= 0 V, f = 1 MHz
V
DS
= 25 V, V
CC
= 0 V, f = 1 MHz
V
DS
= 25 V, V
CC
= 0 V, f = 1 MHz
(V
DS
= 325 V, I
Drain
= 1 A,
V
GS
= 10 V, R
g
= 4.7
W)
(V
DS
= 325 V, I
Drain
= 1.8 A,
V
GS
= 10 V, R
g
= 4.7
W)
(V
DS
= 325 V, I
Drain
= 5.5 A,
V
GS
= 10 V, R
g
= 4.7
W)
I
Drain(off)
V
BR(DSS)
R
DS(on)
−
−
−
−
−
−
C
OSS
–
−
−
−
−
−
−
−
−
2.1
−
5.4
−
9.0
−
67.3
29.2
16.5
4.25
9.32
7.44
5.94
7.54
5.94
2.75
5.0
7.7
13.1
13.2
23.5
–
–
−
−
−
−
−
−
−
pF
–
650
–
–
20
–
mA
V
W
I
CC
= 500
mA
V
CC
= V
CC(on)
– 0.5 V
V
FB
= V
skip
− 0.1 V
I
FB
= 50
mA,
f
SW
= 65 kHz
I
FB
= 50
mA,
f
SW
= 100 kHz
T
J
= –40_C to 125_C
V
V
CC
increasing
V
CC
decreasing
V
CC(on)
− V
CC(off)
V
CC(on)
V
CC(off)
V
CC(HYS)
V
CC(OVP)
t
OVP(delay)
V
ZENER
I
CC1
I
CC2
I
CC3
I
CC4
I
CC(latch)
15.75
7.75
6.0
26.3
–
5
–
–
–
–
42
17
8.5
–
28
26
6.2
–
700
1900
3300
–
20
9.25
–
29.3
–
7.15
15
900
3100
4000
–
mA
V
ms
V
mA
Conditions
Symbol
Min
Typ
Max
Unit
Switching Characteristics
NCP1124
NCP1126
NCP1129
CURRENT SENSE
ns
t
r
t
f
t
r
t
f
t
r
t
f
Current Sense Voltage Threshold
Cycle by Cycle Current Sense
Propagation Delay
NCP1129
NCP1126
NCP1124
Cycle by Cycle Leading Edge Blanking
Duration
INTERNAL OSCILLATOR
Oscillation Frequency
Maximum Duty Ratio
Frequency Jittering in Percentage of f
OSC
V
CS
increasing, T
J
= 25_C
V
CS
increasing
V
CS
dv/dt = 1 V/ms, measured from
V
ILIM1
to DRV falling edge
V
ILIM1
V
ILIM2
t
CS(delay)
730
720
785
800
840
880
mV
ns
–
−
−
t
CS(LEB)
–
100
50
50
320
150
150
150
400
ns
65 kHz Version
100 kHz Version
f
OSC1
f
OSC2
D
MAX
f
jitter
61
92
78
–
65
100
80
±5
71
108
82
–
kHz
%
%
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5
