NCP5212A, NCP5212T
Single Synchronous
Step-Down Controller
The NCP5212A/NCP5212T is a synchronous stepdown controller
for high performance systems battery−power systems. The
NCP5212A/NCP5212T includes a high efficiency PWM controller. A
pin is provided to allow two devices in interleaved operation. An
internal power good voltage monitor tracks the SMPS output.
NCP5212A/NCP5212T also features soft−start sequence, UVLO for
V
CC
and switcher, overvoltage protection, overcurrent protection,
undervoltage protection and thermal shutdown. The IC is packaged in
QFN16
Features
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QFN16
CASE 485AP
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0.8% accuracy 0.8 V Reference
4.5 V to 27 V Battery/Adaptor Voltage Range
Adjustable Output Voltage Range: 0.8 V to 3.3 V
Synchronization Interleaving between Two NCP5212A/NCP5212Ts
Skip Mode for Power Saving Operation at Light Load
Lossless Inductor Current Sensing
Programmable Transient−Response−Enhancement (TRE) Control
Programmable Adaptive Voltage Positioning (AVP)
Input Supply Feedforward Control
Internal Soft−Start
Integrated Output Discharge (Soft−Stop)
Build−in Adaptive Gate Drivers
PGOOD Indication
Overvoltage, Undervoltage and Overcurrent Protections
Thermal Shutdown
QFN16 Package
These Devices are Pb−Free and are RoHS Compliant
MARKING DIAGRAMS
16
1
N5212
ALYWG
G
NCP5212A
N5212/5212T
A
L
Y
W
G
1
16
5212T
ALYWG
G
NCP5212T
Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
PGOOD
SWM
Typical Applications
16
VIN
VCC
SYN
EN
1
2
3
4
5
COMP
15
14
•
Notebook Application
•
System Power
BST
13
12
VCCP
DL/TRESET
PGND
CS+
11
10
9
8
CS−/Vo
NCP5212A/
NCP5212T
6
FB
QFN16
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 18 of this data sheet.
©
Semiconductor Components Industries, LLC, 2009
August, 2009
−
Rev. 3
1
IDRP/OCP
DH
7
Publication Order Number:
NCP5212A/D
NCP5212A, NCP5212T
PGOOD
SWN
BST
13
IDRP/OCP
Detection
High Side
Driver
Over Current
Detector
AVP
Control
12
VCCP
DH
14
TPAD
17
16
PGOOD
15
AGND
Thermal
Shutdown
OSC
VIN
1
VCC
UVLO
Control
UVLO
Control
ENABLE
MASTER
SLAVE
OC & TRE Detection
NCP5212A/NCP5212T
Control Logic, Protection,
RAMP Generator and PWM Logic
VCC
2
Low Side
Driver
11
DL/TRESET
PGH
UVP
SYN
3
OVP
PGL
CDIFF
+
−
+
−
+
−
+
−
10
PGND
−
+
VREF−10%
VREF−20%
EN
4
Level
Control
VREF+15%
DISCH
VREF+10%
Current
Sense
Amplifier
9
CS+
+
VREF
Error
Amplifier
−
5
COMP
6
FB
7
IDRP/OCP
8
CS−/Vo
Figure 1. Detail Block Diagram
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NCP5212A, NCP5212T
VIN
5V
PGOOD
PGOOD
SWN
BST
16
VIN
VCC
SYN
3
EN_SKIP
EN_SKIP
4
5
COMP
1
2
15
DH
VOUT
14
13
12
11
10
9
VCCP
DL/TRESET
PGND
CS+
NCP5212A/NCP5212T
AGND
GND
6
FB
7
IDRP/OCP
8
CS−/Vo
Figure 2. Typical Application Circuit (Single Device Operation)
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NCP5212A, NCP5212T
VIN
5V
PGOOD1
PGOOD
SWN
BST
16
VIN
VCC
SYN
EN=VEN_Master
EN
1
2
3
4
5
COMP
15
DH
VOUT1
GND1
14
13
12
VCCP
DL/TRESET
PGND
CS+
NCP5212A/
NCP5212T
AGND
Master
6
FB
7
IDRP/OCP
8
CS−/Vo
BST
11
10
9
PGOOD2
PGOOD
SWN
16
VIN
VCC
SYN
EN=VEN_Slave
EN
1
2
3
4
5
COMP
15
DH
VOUT2
GND2
14
13
12
VCCP
DL/TRESET
PGND
CS+
NCP5212A/
NCP5212T
AGND
Slave
6
FB
7
IDRP/OCP
8
CS−/Vo
11
10
9
Figure 3. Typical Application Circuit (Dual Device Operation)
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NCP5212A, NCP5212T
PIN FUNCTION DESCRIPTION
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Symbol
VIN
VCC
SYN
EN
COMP
FB
IDRP/OCP
CS−/Vo
CS+
PGND
DL/TRESET
VCCP
BST
DH
SWN
PGOOD
TPAD
Description
Input voltage used for feed forward in switcher operation.
Supply for analog circuit
Synchronization interleaving use.
This pin serves as two functions. Enable: Logic control for enabling the switcher. MASTER/SLAVE: To
program the device as MASTER or SLAVE mode at dual device operation.
Output of the error amplifier.
Output voltage feed back.
Current limit programmable and setting for AVP.
Inductor current differential sense inverting input.
Inductor current differential sense non−inverting input.
Ground reference and high−current return path for the bottom gate driver.
Gate driver output of bottom N−channel MOSFET. It also has the function for TRE threshold setting.
Supply for bottom gate driver.
Top gate driver input supply, a bootstrap capacitor connection between SWN and this pin.
Gate driver output of top N−channel MOSFET.
Switch node between top MOSFET and bottom MOSFET.
Power good indicator of the output voltage. High impendence if power good (in regulation). Low im-
pendence if power not good.
Copper pad on bottom of IC used for heat sinking. This pin should be connected to the analog ground
plane under the IC.
ABSOLUTE MAXIMUM RATINGS
Rating
VCC Power Supply Voltage to AGND
VIN Supply to AGND
High−side Gate Drive Supply: BST to SWN
High−side Gate Drive Voltage: DH to SWN
Low−side Gate Drive Supply: VCCP to PGND
Low−side Gate Drive Voltage: DL to PGND
Input / Output Pins to AGND
Switch Node SWN−PGND
High−Side Gate Drive/Low−Side Gate Drive Outputs
PGND
Thermal Characteristics
Thermal Resistance Junction−to−Ambient (QFN16 Package)
Operating Junction Temperature Range (Note 1)
Operating Ambient Temperature Range
Storage Temperature Range
Moisture Sensitivity Level
Symbol
V
CC
V
IN
V
BST
−V
SWN,
V
DH
−V
SWN,
V
CCP
−V
PGND,
V
DL
−V
PGND,
V
IO
V
SWN
DH, DL
V
PGND
R
qJA
T
J
T
A
T
stg
MSL
Value
−0.3,
6.0
−0.3,
30
−0.3,
6.0
Unit
V
V
V
−0.3,
6.0
−5
V (< 100 ns)
30 V
−3(DC)
−0.3,
0.3
48
−40
to + 150
−
40 to + 85
−
55 to +150
1
V
V
V
V
°C/W
°C
°C
°C
−
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.
1. Internally limited by thermal shutdown, 150°C min.
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