NCP6336
Product Preview
Configurable 5.0 A Step
Down Converter - Transient
Load Helper
The NCP6336 is a synchronous buck converter optimized to supply
the different sub systems of portable applications powered by one cell
Li−Ion or three cell Alkaline/NiCd/NiMH batteries. The device is able
to deliver up to 5.0 A, with programmable output voltage from 0.6 V
to 1.5 V. It can share the same output rail with another DC−to−DC
converter and works as a transient load helper. Operation at a 3 MHz
switching frequency allows the use of small components.
Synchronous rectification and automatic PWM/PFM transitions
improve overall solution efficiency. The NCP6336 is in a space
saving, low profile 2.0 x 1.6 mm CSP−20 package.
Features
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MARKING
DIAGRAM
WLCSP20
CASE 568AG
6336x
AWLYWW
G
x
•
Input Voltage Range from 2.3 V to 5.5 V: Battery and 5 V Rail
•
•
•
•
•
•
•
•
•
•
•
Powered Applications
Programmable Output Voltage: 0.6 V to 1.5 V in 10 mV Steps
3 MHz Switching Frequency with On Chip Oscillator
Uses 330 nH Inductor and 47
mF
Capacitors for Optimized Footprint
and Solution Thickness
PFM/PWM Operation for Optimum Increased Efficiency
Low 35
mA
Quiescent Current
I
2
C Control Interface with Interrupt and Dynamic Voltage Scaling
Support
Enable Pins, Power Good / Fail Signaling
Thermal Protections and Temperature Management
Transient Load Helper: Share the Same Rail with Another Rail
Small 2.0 x 1.6 mm / 0.4 mm Pitch CSP Package
These are Pb−Free Devices
= P: Prototype
= blank: Production
A
= Assembly Location
WL = Wafer Lot
Y
= Year
WW = Work Week
G
= Pb−Free Package
Pb−Free indicator, G or microdot (G), may or may
not be present
PIN OUT
1
2
3
4
A
VSEL
EN
SCL
FB
B
SDA
PGND
INTB*
PGND
PG*
AGND
C
PGND
PGND
PGND
PGND
Typical Applications
•
Smartphones
•
Tablets
AGND
B4
D
AVIN
PVIN
SW
SW
NCP6336
Core
Thermal
Protection
D1
AVIN
E
PVIN
PVIN
SW
SW
PVIN
4.7 uF
Supply Input
D2
E1
E2
(Top View)
*Optional
Enable Control EN
Input
Voltage
Selection
VSEL
A2
A1
Operating
Mode
Control
DCDC
5.0 A
D3
D4
E3
E4
SW
330 nH
ORDERING INFORMATION
47 uF
See detailed ordering and shipping information on page 29 of
this data sheet.
Power Fail
Interrupt
PGND
PG
PGND
INTB
SDA
B3
Output
Monitoring
C1
C2
C3
C4
PGND
B2
B1
Processor
@
C
I
Control Interface SCL
I@C
DCDC
3 MHz
Controller
A4
FB
Sense
Processor
Core
A3
Figure 1. Typical Application Circuit
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
©
Semiconductor Components Industries, LLC, 2014
1
April, 2014 − Rev. P2
Publication Order Number:
NCP6336/D
NCP6336
PVIN
PVIN
PVIN
SUPPLY INPUT
ANALOG GROUND
POWER
INPUT
AVIN
AGND
Core
Thermal
Protection
5.0 A
DC−DC
SW
SW
SW
SW
SWITCH
NODE
POWER GOOD
(optional)
PG
Output Voltage
Monitoring
ENABLE CONTROL INPUT
EN
VOLTAGE SELECTION
VSEL
Operating
Mode Control
3 MHz DC−DC
converter
Controller
PGND
PGND
PGND
PGND
FB
POWER
GROUND
INTERRUPT OUTPUT
(optional)
PROCESSOR I C
CONTROL INTERFACE
2
INTB
SCL
SDA
Logic Control
Interrupt
I2C
Sense
FEEDBACK
Figure 2. Simplified Block Diagram
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2
NCP6336
1
2
3
4
A
VSEL
EN
SCL
FB
B
SDA
PGND
INTB*
PGND
PG*
AGND
C
PGND
PGND
PGND
PGND
D
AVIN
PVIN
SW
SW
E
PVIN
PVIN
SW
SW
*Optional
Figure 3. Pin Out (Top View)
PIN FUNCTION DESCRIPTION
Pin
REFERENCE
D1
AVIN
Analog Input
Analog Supply.
This pin is the device analog and digital supply. Could be connected
directly to the VIN plane just next to the 4.7
mF
PVIN capacitor or to a dedicated
1.0
mF
ceramic capacitor.
Analog Ground.
Analog and digital modules ground. Must be connected to the sys-
tem ground.
Name
Type
Description
B4
AGND
Analog Ground
CONTROL AND SERIAL INTERFACE
A2
A1
EN
VSEL
Digital Input
Digital Input
Enable Control.
Active high will enable the part. There is an internal pull down resist-
or on this pin.
Output voltage / Mode Selection.
The level determines which of two programmable
configurations to utilize (operating mode / output voltage). There is an internal pull
down resistor on this pin; could be left open if not used.
I
2
C interface
Clock
line. There is an internal pull down resistor on this pin; could be
left open if not used
I
2
C interface Bi−directional
Data
line. There is an internal pull down resistor on this
pin; could be left open if not used
Power Good
open drain output. If not used has to be connected to ground plane
Interrupt
open drain output. If not used has to be connected to ground plane
A3
B1
B3
B2
SCL
SDA
PGND
PG
PGND
INTB
Digital Input
Digital
Input/Output
Digital Output
Analog Ground
Digital Output
Analog Ground
DC to DC CONVERTER
D2, E1, E2
PVIN
Power Input
Switch Supply.
These pins must be decoupled to ground by a 4.7
mF
ceramic capa-
citor. It should be placed as close as possible to these pins. All pins must be used
with short heavy connections.
Switch Node.
These pins supply drive power to the inductor. Typical application uses
0.33
mH
inductor; refer to application section for more information.
All pins must be used with short heavy connections.
Switch Ground.
This pin is the power ground and carries the high switching current.
High quality ground must be provided to prevent noise spikes. To avoid high−density
current flow in a limited PCB track, a local ground plane that connects all PGND pins
together is recommended. Analog and power grounds should only be connected
together in one location with a trace.
Feedback Voltage input.
Must be connected to the output capacitor positive termin-
al with a trace, not to a plane. This is the positive input to the error amplifier.
D3, D4,
E3, E4
C1, C2,
C3, C4
SW
Power Output
PGND
Power Ground
A4
FB
Analog Input
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3
NCP6336
MAXIMUM RATINGS
Rating
Analog and power pins: AVIN, PVIN, SW, PG, INTB, FB (Note 1)
Digital pins: SCL, SDA, EN, VSEL, Pin:
Input Voltage
Input Current
Human Body Model (HBM) ESD Rating (Note 2)
Charged Device Model (CDM) ESD Rating (Note 2)
Latch Up Current: (Note 3)
Digital Pins
All Other Pins
Storage Temperature Range
Maximum Junction Temperature
Moisture Sensitivity (Note 4)
Symbol
V
A
V
DG
I
DG
ESD HBM
ESD CBM
I
LU
10
100
T
STG
T
JMAX
MSL
−65 to +150
−40 to +150
Level 1
°C
°C
Value
−0.3 to + 6.0
−0.3 to V
A
+ 0.3
≤
6.0
10
2500
1250
Unit
V
V
mA
V
V
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe
Operating parameters.
2. This device series contains ESD protection and passes the following ratings:
Human Body Model (HBM)
±
2.5 kV per JEDEC standard: JESD22−A114.
Charged Device Model (CDM)
±
1250 V per JEDEC standard: JESD22−C101 Class IV
3. Latch up Current per JEDEC standard: JESD78 class II.
4. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.
OPERATING CONDITIONS
Symbol
AV
IN,
PV
IN
T
A
T
J
R
qJA
P
D
P
D
L
Co
Cin
Power Supply
Ambient Temperature Range
Junction Temperature Range (Note 6)
Thermal Resistance Junction to Ambient (Note 7)
Power Dissipation Rating (Note 8)
Power Dissipation Rating (Note 8)
Inductor for DC to DC converter (Note 5)
Output Capacitor for DC to DC Converter (Note 5)
Input Capacitor for DC to DC Converter (Note 5)
CSP−20 on Demo−board
T
A
≤
85°C
T
A
= 65°C
Parameter
Conditions
Min
2.3
−40
−40
−
−
−
0.26
30
4.7
25
25
55
727
1090
0.33
−
−
Typ
Max
5.5
+85
+125
−
−
−
0.56
150
−
Unit
V
°C
°C
°C/W
mW
mW
mH
mF
mF
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
5. Including de−ratings (Refer to the Application Information section of this document for further details)
6. The thermal shutdown set to 150°C (typical) avoids potential irreversible damage on the device due to power dissipation.
7. The R
qJA
is dependent of the PCB heat dissipation. Board used to drive this data was a NCP6336EVB board. It is a multilayer board with
1−once internal power and ground planes and 2−once copper traces on top and bottom of the board.
8. The maximum power dissipation (P
D
) is dependent by input voltage, maximum output current and external components selected.
R
qJA
+
125
*
T
A
P
D
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4
NCP6336
ELECTRICAL CHARACTERISTICS
(Notes 10 and 11)
Min and Max Limits apply for T
A
= −40°C to +85°C, AVIN = PVIN = 3.6 V and default configuration, unless otherwise specified.
Typical values are referenced to T
A
= +25°C, AVIN = PVIN = 3.6 V and default configuration, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
SUPPLY CURRENT: PINS AVIN – PVINx
I
Q PWM
I
Q PFM
I
SLEEP
Operating quiescent current PWM
Operating quiescent current PFM
Product sleep mode current
DCDC active in Forced PWM
no load
DCDC active in Auto mode
no load − minimal switching
EN high, DCDC off or
EN low and (VSEL high or
Sleep_Mode high)
V
IN
= 2.5 V to 5.5 V
EN, VSEL and Sleep_Mode low
V
IN
= 2.5 V to 5.5 V
−
−
−
15
35
7
25
70
15
mA
mA
mA
I
OFF
Product in off mode
−
0.8
5
mA
DC to DC CONVERTER
PV
IN
I
OUTMAX
Input Voltage Range
Maximum Output Current
Ipeak[1..0] = 00 (Note 12)
Ipeak[1..0] = 01 (Note 12)
Ipeak[1..0] = 10 (Note 12)
Ipeak[1..0] = 11 (Note 12)
D
VOUT
Output Voltage DC Error
Forced PWM mode, No load
Forced PWM mode, V
IN
range,
I
OUT
up to I
OUTMAX
(Note 12)
Auto mode, V
IN
range,
I
OUT
up to I
OUTMAX
(Note 12)
F
SW
R
ONHS
R
ONLS
I
PK
Switching Frequency
P−Channel MOSFET On
Resistance
N−Channel MOSFET On
Resistance
Peak Inductor Current
From PVIN to SW
V
IN
= 5.0 V
From SW to PGND
V
IN
= 5.0 V
Open loop – Ipeak[1..0] = 00 (Note 12)
Open loop – Ipeak[1..0] = 01 (Note 12)
Open loop – Ipeak[1..0] = 10 (Note 12)
Open loop – Ipeak[1..0] = 11
DC
LOAD
DC
LINE
Load Regulation
Line Regulation
I
OUT
from 0 A to I
OUTMAX
(Note 12)
Forced PWM mode
I
OUT
= 3 A
2.3 V
≤
V
IN
≤
5.5 V (Note 12)
Forced PWM mode
tr = ts = 100 ns
Load step 1.2 A (Note 12)
2.3
3.5
4.0
4.5
5.0
−1
−1
−1
2.70
−
−
−
−
−
6.1
−
−
−
−
−
−
−
−
−
−
3
23
12
5.2
5.8
6.2
6.8
−0.2
0
5.5
−
−
−
−
1
1
2
3.30
40
20
−
−
−
7.8
−
−
%/A
%
MHz
mW
mW
A
%
V
A
AC
LOAD
D
t
START
Transient Load Response
Maximum Duty Cycle
Turn on time
−
−
±40
100
90
−
−
110
mV
%
ms
Time from EN transitions from Low to
High to 90% of Output Voltage
(DELAY[2..0] = 000b)
V
OUT
= 1.15 V
−
R
DISDCDC
DCDC Active Output Discharge
−
25
35
W
9. Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Prod-
uct performance may not be indicated by the Electrical Characteristics if operated under different conditions.
10. Refer to the Application Information section of this data sheet for more details.
11. Devices that use non−standard supply voltages which do not conform to the intent I
2
C bus system levels must relate their input levels
to the V
DD
voltage to which the pull−up resistors R
P
are connected.
12. Guaranteed by design and characterized.
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5
模拟电子
