NCV891330
3 A, 2 MHz Low-I
Q
Dual-
Mode Step-Down Regulator
for Automotive
The NCV891330 is a Dual Mode regulator intended for Automotive,
battery−connected applications that must operate with up to a 45 V
input supply. Depending on the output load, it operates either as a PWM
Buck Converter or as a Low Drop−Out Linear Regulator, and is suitable
for systems with low noise and Low Quiescent Current requirements
often encountered in automotive driver information systems. A reset
pin (with fixed delay) simplifies interfacing with a microcontroller.
The NCV891330 also provides several protection features expected
in automotive power supply systems such as current limit, short circuit
protection, and thermal shutdown. In addition, the high switching
frequency produces low output voltage ripple even when using small
inductor values and an all−ceramic output filter capacitor – forming a
space−efficient switching regulator solution.
Features
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8
1
SOIC−8
EXPOSED PAD
CASE 751AC
MARKING DIAGRAM
8
891330XX
ALYW
G
1
With XX = 33 for 3.3 V Output
=
38 for 3.8 V Output
=
40 for 4.0 V Output
=
50 for 5.0 V Output
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Device
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
30
mA
Iq in Light Load Condition
3.0 A Maximum Output Current in PWM Mode
Internal N−channel Power Switch
V
IN
Operating Range 3.7 V to 36 V
Withstands Load Dump to 45 V
Logic Level Enable Pin can be Tied to Battery
Fixed Output Voltage of 5.0 V, 4.0 V, 3.8 V or 3.3 V
2 MHz Free−running Switching Frequency
±2
% Output Voltage Accuracy
NCV Prefix for Automotive Requiring Site and Control Changes
These Devices are Pb−Free and are RoHS Compliant
Typical Applications
PIN CONNECTIONS
VIN
DRV
RSTB
CDRV
NCV891330
DBST
L1
VOUT
COUT
GND
1
2
3
4
(Top View)
8
7
6
5
SW
BST
VOUT
EN
Audio
Infotainment
Instrumentation
Safety−Vision Systems
VIN
VIN
CIN
RESET
RSTB
GND
VOUT
EN
EN
DRV
SW
BST
CBST
DFW
ORDERING INFORMATION
See detailed ordering and shipping information on page 15 of
this data sheet.
Figure 1. Typical Application
©
Semiconductor Components Industries, LLC, 2015
1
March, 2017 − Rev. 3
Publication Order Number:
NCV891330/D
NCV891330
CDRV
DBST
VIN
CIN
3.3 V
Reg
DRV
Oscillator
Enable
+
+
S
comp
TSD
VOLTAGES
MONITORS
Switcher Supply
ON
LINEAR
REGULATOR
ON OVLD
3A
detector
Soft−Start
RESET
+
−
EN
+
−
+
EN
Low
PWM
LOGIC
ON OFF
VOUT
BST
CBST
DFW
COUT
VIN
SW
L1
VOUT
RESET
RSTB
GND
Logic
NCV891330
Figure 2. Simplified Block Diagram
Table 1. PIN FUNCTION DESCRIPTION
Pin No.
1
2
3
4
5
6
7
8
EPAD
Pin Name
VIN
DRV
RSTB
GND
EN
VOUT
BST
SW
Description
Input voltage from battery. Place an input filter capacitor in close proximity to this pin.
Output voltage to provide a regulated voltage to the Power Switch gate driver.
Reset function. Open drain output, pulling down to ground when the output voltage is out of regulation.
Battery return, and output voltage ground reference.
This TTL compatible Enable input allows the direct connection of Battery as the enable signal. Grounding
this input stops switching and reduces quiescent current draw to a minimum.
Output voltage feedback and LDO output. Feedback of output voltage used for regulation, as well as LDO
output in LDO mode.
Bootstrap input provides drive voltage higher than VIN to the N−channel Power Switch for minimum
switch Rdson and highest efficiency.
Switching node of the Regulator. Connect the output inductor and cathode of the freewheeling diode to
this pin.
Connect to Pin 4 (electrical ground) and to a low thermal resistance path to the ambient temperature
environment.
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2
+
−
MODE
SELECTION
+
NCV891330
Table 2. ABSOLUTE MAXIMUM RATINGS
Rating
Min/Max Voltage VIN
Max Voltage VIN to SW
Min/Max Voltage SW
Min Voltage SW − 20 ns
Min/Max Voltage EN
Min/Max Voltage BST
Min/Max Voltage BST to SW
Min/Max Voltage on RSTB
Min/Max Voltage VOUT
Min/Max Voltage DRV
Thermal Resistance, SOIC8−EP Junction–to–Ambient (Note 1)
Storage Temperature range
Operating Junction Temperature Range
ESD withstand Voltage (Note 2)
Moisture Sensitivity
Peak Reflow Soldering Temperature (Note 3)
Human Body Model
T
J
VESD
MSL
R
θJA
Symbol
Value
−0.3 to 45
45
−0.7 to 40
−3.0
−0.3 to 40
−0.3 to 43
−0.3 to 3.6
−0.3 to 6
−0.3 to 18
−0.3 to 3.6
30
−55 to +150
−40 to +150
2.0
Level 2
260
°C
Unit
V
V
V
V
V
V
V
V
V
V
°C/W
°C
°C
kV
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Value based on 4 layers of 645 mm
2
(or 1 in
2
) of 1 oz copper thickness on FR4 PCB substrate.
2. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
Latchup Current Maximum Rating:
v150
mA per JEDEC standard: JESD78
3. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
Table 3. ELECTRICAL CHARACTERISTICS
V
IN
= 4.5 to 28 V, V
EN
= 5 V, V
BST
= V
SW
+ 3 V, C
DRV
= 0.1
mF,
for typical values T
J
= 25°C, Min/Max values are valid for the temperature
range −40°C
v
T
J
v
150°C unless noted otherwise, and are guaranteed by test, design or statistical correlation (Notes 4, 5)
Parameter
QUIESCENT CURRENT
Quiescent Current, enabled
Quiescent Current, shutdown
UNDERVOLTAGE LOCKOUT – VIN (UVLO)
UVLO Start Threshold
UVLO Stop Threshold
UVLO Hysteresis
SOFT−START (SS)
Soft−Start Completion Time
OUTPUT VOLTAGE
Output Voltage during regulation
100
mA
< I
OUT
< 2.5 A
5.0 V option
4.0 V option
3.8 V option
3.3 V option
V
OUTreg
4.9
3.92
3.724
3.234
5.0
4.0
3.8
3.3
5.1
4.08
3.876
3.366
V
t
SS
0.8
1.4
2.0
ms
V
IN
rising
V
IN
falling
V
UVLSTT
V
UVLSTP
V
UVLOHY
4.1
3.1
0.4
4.5
3.7
1.4
V
V
V
V
IN
= 13.2 V, I
OUT
= 100
mA,
25°C
V
IN
= 13.2 V, V
EN
= 0 V, 25°C
I
q
I
qSD
30
9
39
12
mA
mA
Test Conditions
Symbol
Min
Typ
Max
Unit
OSCILLATOR
Frequency
4.5 < V
IN
< 18 V
20 V <V
IN
< 28V
F
SW
F
SW(HV)
1.8
0.9
2.0
1.0
2.2
1.1
MHz
4. Refer to ABSOLUTE MAXIMUM RATINGS and APPLICATION INFORMATION for Safe Operating Area.
5. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at T
J
= T
A
= 25°C. Low
duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
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NCV891330
Table 3. ELECTRICAL CHARACTERISTICS
V
IN
= 4.5 to 28 V, V
EN
= 5 V, V
BST
= V
SW
+ 3 V, C
DRV
= 0.1
mF,
for typical values T
J
= 25°C, Min/Max values are valid for the temperature
range −40°C
v
T
J
v
150°C unless noted otherwise, and are guaranteed by test, design or statistical correlation (Notes 4, 5)
Parameter
VIN FREQUENCY FOLDBACK MONITOR
Frequency Foldback Threshold
V
IN
rising
V
IN
falling
Frequency Foldback Hysteresis
MODE TRANSITION
Normal to Low−Iq mode Current Threshold
Mode Transition Duration
Switcher to Linear
Linear to Switcher
Minimum time in Normal Mode before
starting to monitor output current
Linear to switcher transition
at high Vin
at low Vin
PEAK CURRENT LIMIT
Current Limit Threshold
POWER SWITCH
ON Resistance
Leakage current VIN to SW
Minimum ON Time
Minimum OFF Time
V
BST
= V
SW
+ 3.0 V
V
SW
= 0, −40°C
v
T
J
v
85°C
Measured at SW pin
Measured at SW pin
At F
SW
= 2 MHz (normal)
At F
SW
= 500 kHz (max duty cycle)
R
DSON
I
LKSW
t
ONMIN
t
OFFMIN
30
30
50
70
45
180
360
10
70
mW
mA
ns
ns
I
LIM
3.9
4.4
4.9
A
V
OUT
= 3.3 V
V
LINtoSW(HV)
V
LINtoSW(LV)
19
3.6
28
4.5
8 V < V
IN
< 28 V
I
NtoL
t
SWtoLIN
t
LINtoSW
t
SWblank
3
300
1
500
40
mA
ms
2
ms
V
V
V
FLDUP
V
FLDDN
V
FLDHY
18.4
18
0.2
0.3
20
19.8
0.4
V
Test Conditions
Symbol
Min
Typ
Max
Unit
SLOPE COMPENSATION
Ramp Slope
(With respect to switch current)
LOW POWER LINEAR REGULATOR
Line Regulation
Load Regulation
Power Supply Rejection
Current Limit
Output clamp current
SHORT CIRCUIT DETECTOR
Switching frequency in short−circuit condi-
tion
Analog Foldback
Analog foldback – high V
IN
Hiccup Mode
RESET
Leakage current into RSTB pin
Output voltage threshold at which the RSTB V
OUT
decreasing
signal goes low
5.0 V option
4.0 V option
3.8 V option
3.3 V option
I
RSTBlk
V
RESET
4.50
3.6
3.42
2.97
4.625
3.7
3.515
3.05
4.75
3.8
3.61
3.14
1
uA
V
kHz
V
OUT
= 0 V, 4.5 V < V
IN
< 18 V
V
OUT
= 0 V, 20 V <V
IN
< 28 V
F
SWAF
F
SWAFHV
F
SWHIC
450
225
24
550
275
32
650
325
40
V
OUT
= V
OUTreg(typ)
+ 10%
I
OUT
= 5 mA, 6 V < V
IN
< 18 V
V
IN
= 13.2 V, 0.1 mA < I
OUT
< 50 mA
V
OUT(ripple)
= 0.5 Vp−p, F = 100 Hz
V
REG(line)
V
REG(load)
PSRR
I
LIN(lim)
I
CL(OUT)
50
0.5
1.0
5
5
65
80
1.5
25
35
mV
mV
dB
mA
mA
4.5 < V
IN
< 18 V
20 V <V
IN
< 28V
S
ramp
S
ramp(HV)
1.45
0.65
2.0
1.0
2.8
1.3
A/ms
4. Refer to ABSOLUTE MAXIMUM RATINGS and APPLICATION INFORMATION for Safe Operating Area.
5. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at T
J
= T
A
= 25°C. Low
duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
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NCV891330
Table 3. ELECTRICAL CHARACTERISTICS
V
IN
= 4.5 to 28 V, V
EN
= 5 V, V
BST
= V
SW
+ 3 V, C
DRV
= 0.1
mF,
for typical values T
J
= 25°C, Min/Max values are valid for the temperature
range −40°C
v
T
J
v
150°C unless noted otherwise, and are guaranteed by test, design or statistical correlation (Notes 4, 5)
Parameter
RESET
Hysteresis on RSTB threshold
V
OUT
increasing
5.0 V option
4.0 V option
3.8 V option
3.3 V option
From V
OUT
<V
RESET
to RSTB pin
going low
From V
OUT
>V
RESET
+V
REShys
to
high RSTB
V
REShys
25
20
19
17
t
filter
t
delay
10
14
16
60
50
45
40
100
80
76
66
25
18
0.4
ms
ms
V
mV
Test Conditions
Symbol
Min
Typ
Max
Unit
Noise−filtering delay
Restart Delay time
Low RSTB voltage
GATE VOLTAGE SUPPLY (DRV pin)
Output Voltage
DRV UVLO START Threshold
DRV UVLO STOP Threshold
DRV UVLO Hysteresis
DRV Current Limit
R
RSTBpullup
= V
OUTreg
/1 mA, V
OUT
> 1 V V
RSTBlow
V
DRV
V
DRVSTT
V
DRVSTP
V
DRVHYS
V
DRV
= 0 V
I
DRVLIM
3.1
2.7
2.5
50
21
3.3
2.9
2.8
3.5
3.05
3.0
200
50
V
V
V
mV
mA
VIN OVERVOLTAGE SHUTDOWN MONITOR
Overvoltage Stop Threshold
Overvoltage Start Threshold
Overvoltage Hysteresis
ENABLE (EN)
Logic low threshold voltage
Logic high threshold voltage
EN pin input current
THERMAL SHUTDOWN
Activation Temperature
Reset temperature
Hysteresis
TSD
TSD
restart
T
HYS
155
135
5
190
185
20
°C
°C
°C
V
ENlow
V
ENhigh
I
ENbias
0.2
0.8
2
1
V
V
mA
V
IN
increasing
V
IN
decreasing
V
OVSTP
V
OVSTT
V
OVHY
36.5
36.0
0.25
37.7
37.3
0.40
39.0
38.8
0.50
V
V
V
4. Refer to ABSOLUTE MAXIMUM RATINGS and APPLICATION INFORMATION for Safe Operating Area.
5. Performance guaranteed over the indicated operating temperature range by design and/or characterization tested at T
J
= T
A
= 25°C. Low
duty cycle pulse techniques are used during testing to maintain the junction temperature as close to ambient as possible.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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DSP 与 ARM 处理器
