Philips Semiconductors Linear Products
Product specification
Sample-and-hold amplifier
NE/SE5537
DESCRIPTION
The NE5537 monolithic sample-and-hold amplifier combines the
best features of ion-implanted JFETs with bipolar devices to obtain
high accuracy, fast acquisition time, and low droop rate. This device
is pin-compatible with the LF198, and features superior performance
in droop rate and output drive capability. The circuit shown in Figure
1 contains two operational amplifiers which function as a unity gain
amplifier in the sample mode. The first amplifier has bipolar input
transistors which give the system a low offset voltage. The second
amplifier has JFET input transistors to achieve low leakage current
from the hold capacitor. A unique circuit design for leakage current
cancellation using current mirrors gives the NE5537 a low droop
rate at higher temperature. The output stage has the capability to
drive a 2kΩ load. The logic input is compatible with TTL, PMOS or
CMOS logic. The differential logic threshold is 1.4V with the sample
mode occurring when the logic input is high. It is available in 8-lead
TO-5, 8-pin plastic DIP packages, and 14-pin SO packages.
PIN CONFIGURATIONS
FE and N Packages
V+ 1
OFFSET ADJUST 2
INPUT 3
V– 4
8
7
6
5
LOGIC
LOGIC REFERENCE
C
h
OUTPUT
D
1
Package
INPUT
NC
V–
NC
NC
1
2
3
4
5
6
7
14
V
OS
ADJ
13
NC
12
V+
11
LOGIC
10
LOGIC REFERENCE
9
8
NC
C
h
FEATURES
NC
OUTPUT
•
Operates from
±5V
to
±18V
supplies
•
Hold leakage current 6pA @ T
J
= 25°C
•
Less than 4µs acquisition time
•
TTL, PMOS, CMOS compatible logic input
•
0.5mV typical hold step at CH=0.01µF
•
Low input offset: 1MV (typical)
•
0.002% gain accuracy with R
L
=2kΩ
•
Low output noise in hold mode
•
Input characteristics do not change during hold mode
•
High supply rejection ratio in sample or hold
•
Wide bandwidth
NOTE:
1. SO and non-standard pinouts.
BLOCK DIAGRAM
OFFSET
2
30k
5
–
3
+
OUTPUT
INPUT
LOGIC
8
–
+
300
7
LOGIC
REFERENCE
6
HOLD
CAPACITOR
ORDERING INFORMATION
DESCRIPTION
8-Pin Plastic Dual In-Line Package (DIP)
14-Pin Plastic Small Outline (SO) Package
8-Pin Plastic Dual In-Line Package (DIP)
TEMPERATURE RANGE
0 to +70°C
0 to +70°C
-55°C to +125°C
ORDER CODE
NE5537N
NE5537D
SE5537FE
DWG #
0404B
0175D
0404B
August 31, 1994
884
853-1044 13721
Philips Semiconductors Linear Products
Product specification
Sample-and-hold amplifier
NE/SE5537
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
S
P
D
Voltage supply
Maximum power dissipation
T
A
=25°C (still-air)
1
N package
D package
FE package
T
A
Operating ambient temperature range
SE5537
NE5537
T
STG
V
IN
Storage temperature range
Input voltage
Logic to logic reference differential voltage
2
Output short circuit duration
Hold capacitor short circuit duration
T
SOLD
Lead soldering temperature (10sec max)
-55 to +125
0 to +70
-65 to +150
Equal to supply voltage
+7, -30
Indefinite
10
300
s
°C
V
°C
°C
°C
1160
1090
780
mW
mW
mW
PARAMETER
RATING
±18
UNIT
V
NOTES:
1. Derate above 25°C at the following rates:
FE package at 6.2mW/°C
N package at 9.3mW/°C
D package at 8.3mW/°C
2. Although the differential voltage may not exceed the limits given, the common-mode voltage on the logic pins may be equal to the supply
voltages without causing damage to the circuit. For proper logic operation, however, one of the logic pins must always be at least 2V below
the positive supply and 3V above the negative supply.
August 31, 1994
885
Philips Semiconductors Linear Products
Product specification
Sample-and-hold amplifier
NE/SE5537
DC ELECTRICAL CHARACTERISTICS
1
SYMBOL
PARAMETER
TEST CONDITIONS
T
J
=25°C
V
OS
Input offset
voltage
4
Full temperature range
T
J
=25°C
I
BIAS
Input bias
current
4
Full temperature range
Input impedance
Gain error
T
J
=25°C
T
J
=25°C
-10V≤V
IN
≤10V,
R
L
=2kΩ
-11.5V≤V
IN
≤11.5V,
R
L
=10kΩ
Full temperature range
Feedthrough attenuation
ratio at 1kHz
Output impedance
“HOLD” Step
2
I
CC
Supply
current
4
Logic and logic reference
input current
Leakage current into hold
capacitor
4
Acquisition time to 0.1%
T
J
=25°C
T
J
=25°C “hold” mode
3
V
OUT
=10V,
C
H
=1000pF
C
H
=0.01µF
Hold capacitor charging
current
SVRR
Supply voltage rejection
ratio
Differential logic threshold
V
IN
-V
OUT
=2V
V
OUT
=0V
T
J
=25°C
80
0.8
2
6
4
20
5
110
1.4
2.4
80
0.8
10
50
2
6
4
20
5
110
1.4
2.4
10
100
µA
pA
µs
µs
mA
dB
V
T
J
=25°C, C
H
=0.01µF
T
J
=25°C, “HOLD” mode
Full temperature range
T
J
=25°C, C
H
=0.01µF, V
OUT
=0
T
J
=25°C
0.5
4.5
86
96
0.5
2
4
2.0
6.5
1.0
4.5
0.02
80
90
0.5
4
6
2.5
7.5
mV
mA
0.02
%
dB
Ω
10
10
0.002 0.007
75
10
10
0.004
0.01
100
nA
Ω
%
5
5
25
10
10
50
mV
nA
SE5537
Min
Typ
1
Max
3
Min
NE5537
Typ
2
Max
7
UNIT
mV
NOTES:
1. Unless otherwise specified, the following conditions apply: Unit is in “sample” mode. V
S
=±15V, T
J
=25°C, -11.5V≤V
IN
≤11.5V,
C
H
=0.01µF, and
R
L
=2kΩ. Logic reference voltage=0V and logic voltage=2.5V.
2. Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. 1pF, for instance, will create an
additional 0.5mV step with a 5V logic swing and a 0.01F hold capacitor. Magnitude of the hold step is inversely proportional to hold capacitor
value.
3. Leakage current is measured at a junction temperature of 25°C. The effects of junction temperature rise due to power dissipation or elevated
ambient can be calculated by doubling the 25°C value for each 11°C increase in chip temperature. Leakage is guaranteed over full input
signal range.
4. These parameters guaranteed over a supply voltage range of
±5
to
±18V.
August 31, 1994
886
Philips Semiconductors Linear Products
Product specification
Sample-and-hold amplifier
NE/SE5537
TYPICAL PERFORMANCE CHARACTERISTICS
Input Bias Current
25
20
15
CURRENT (mA)
CURRENT (nA)
24
22
20
SINKING
18
16
14
–10
–15
–50
12
–25
0
25
50
75
100
125
150
10
–50
–25
0
25
50
75
100
125
150
10
5
0
–5
SOURCING
30
28
26
Output Short-Circuit Current
INPUT VOLTAGE — OUTPUT VOLTAGE (mV)
1
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
–15
–10
Gain Error
T
J
= 25°C
R
L
= 2kΩ
SAMPLE MODE
–5
0
5
10
15
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
INPUT VOLTAGE (V)
Hold Step
100
V+ = V– = 15V
T
J
= 25°C
HOLD STEP (mV)
10
CURRENT (nA)
1
10
Leakage Current Into
Hold Capacitor
2
NORMALIZED HOLD STEP AMPLITUDE
V
S
=
±15V
V
OUT
= 0
HOLD MODE
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
Hold Step vs Input Voltage
T
J
= 100°C
1
10
–1
T
J
= 25°C
0.1
10
–2
T
J
= –55°C
0.01
100pF
10
–3
1000pF
0.01µF
0.1µF
1µF
–50
–25
0
25
50
75
100
125
150
0
–15
–10
–5
0
5
10
15
HOLD CAPACITOR
JUNCTION TEMPERATURE (°C)
INPUT VOLTAGE (V)
Acquisition Time
1
V
IN
= 0 TO
±10V
T
J
= 25°C
1%
TIME (
µ
s)
0.1%
TIME (ns)
10
250
225
200
175
150
125
100
75
50
25
1000
0.001
0
0.01
HOLD CAPACITOR (µF)
0.1
–50
–25
Aperture Time
100
V+ = V– = 15V
∆V
OUT
≤
1mV
FINAL SAG (mV)
∆V
IN
– 10V
10
Capacitor Hysteresis
MYLAR
HYSTERESIS
POLYPROPYLENE
AND POLYSTYRENE
TIME CONSTANT
NEGATIVE
INPUT
STEP
0.01%
100
1
MYLAR
TIME
CONSTANT
0.1
POLYPROPYLENE
AND POLYSTYRENE
HYSTERSIS
1
10
100
POSITIVE
INPUT
STEP
0
25
50
75
100 125 150
0.1
JUNCTION TEMPERATURE (°C)
SAMPLE TIME (ms)
August 31, 1994
887
Philips Semiconductors Linear Products
Product specification
Sample-and-hold amplifier
NE/SE5537
TYPICAL PERFORMANCE CHARACTERISTICS
(Continued)
Dynamic Sampling Error
100
330pF
10
0
Output Droop Rate
2
1.8
Hold Settling Time
V+ = V– = 15V
SETTLING TO 1mV
10
ERROR (mV)
∆
V/
∆
T (V/SEC)
TIME (
µ
S)
1µF
0.01µF
0.033µF
0.1µF
0.03µF
3300pF
1000pF
10
–1
1.6
1.4
T
J
= 85°C
1.2
1
0.8
0.6
0.4
0.2
±1
10
–2
–10
10
–3
T
J
= 25°C
–100
0.1
10
–4
1
10
100
1000
100pF
1000pF
0.01µF
0.1µF
0
–50 –25
0
25
50
75 100 125 150
INPUT SLEW RATE (V/ms)
HOLD CAPACITOR
JUNCTION TEMPERATURE (°C)
Phase and Gain
(Input-to-Output, Small-Signal)
INPUT TO OUTPUT PHASE DELAY (DEG)
5
GAIN—INPUT TO OUTPUT (dB)
0
–5
–10
80
70
60
50
40
30
20
10
1k
1M
0
10M
160
140
120
REJECTION (dB)
100
80
60
40
20
0
100
Power Supply Rejection
160
T
J
= 25°C
V+ = V– = 15V
V
OUT
= 0V
Hz)
140
120
100
Output Noise
NOISE (nV/
POSITIVE
SUPPLY
NEGATIVE
SUPPLY
“HOLD” MODE
80
60
40
20
0
SAMPLE MODE
10k
100k
FREQUENCY (Hz)
1k
10k
100k
1M
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Feedthrough Rejection
Ratio (Hold Mode)
–130
–120
–110
RATIO (dB)
–100
–90
–80
C
h
= 1000pF
–70
–60
–50
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
C
h
= 0.01µF
C
h
= 0.1µF
V+ = V– = 15V
V
IN
= 10V
P-P
V
7,8
= 0
T
J
= 25°C
August 31, 1994
888
