376
TM
HIGH PERFORMANCE
32-BIT EMBEDDED PROCESSOR
Y
Full 32-Bit Internal Architecture
8- 16- 32-Bit Data Types
8 General Purpose 32-Bit Registers
Extensive 32-Bit Instruction Set
High Performance 16-Bit Data Bus
16 or 20 MHz CPU Clock
Two-Clock Bus Cycles
16 Mbytes Sec Bus Bandwidth
16 Mbyte Physical Memory Size
High Speed Numerics Support with the
80387SX
Low System Cost with the 82370
Integrated System Peripheral
On-Chip Debugging Support Including
Break Point Registers
Y
Y
Complete Intel Development Support
C PL M Assembler
ICE
TM
-376 In-Circuit Emulator
iRMK Real Time Kernel
iSDM Debug Monitor
DOS Based Debug
Extensive Third-Party Support
Languages C Pascal FORTRAN
BASIC and ADA
Hosts VMS UNIX MS-DOS and
Others
Real-Time Kernels
High Speed CHMOS IV Technology
Available in 100 Pin Plastic Quad Flat-
Pack Package and 88-Pin Pin Grid Array
(See Packaging Outlines and Dimensions
231369)
Y
Y
Y
Y
Y
Y
Y
INTRODUCTION
The 376 32-bit embedded processor is designed for high performance embedded systems It provides the
performance benefits of a highly pipelined 32-bit internal architecture with the low system cost associated with
16-bit hardware systems The 80376 processor is based on the 80386 and offers a high degree of compatibil-
ity with the 80386 All 80386 32-bit programs not dependent on paging can be executed on the 80376 and all
80376 programs can be executed on the 80386 All 32-bit 80386 language translators can be used for
software development With proper support software any 80386-based computer can be used to develop and
test 80376 programs In addition any 80386-based PC-AT compatible computer can be used for hardware
prototyping for designs based on the 80376 and its companion product the 82370
240182 – 48
80376 Microarchitecture
Intel iRMK ICE 376 386 Intel386 iSDM Intel1376 are trademarks of Intel Corp
UNIX is a registered trademark of AT T
ADA is a registered trademark of the U S Government Ada Joint Program Office
PC-AT is a registered trademark of IBM Corporation
VMS is a trademark of Digital Equipment Corporation
MS-DOS is a trademark of MicroSoft Corporation
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT
INTEL CORPORATION 1995
December 1990
Order Number 240182-004
376 EMBEDDED PROCESSOR
1 0 PIN DESCRIPTION
240182– 52
Figure 1 1 80376 100-Pin Quad Flat-Pack Pin Out (Top View)
Table 1 1 100-Pin Plastic Quad Flat-Pack Pin Assignments
Address
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
A
19
A
20
A
21
A
22
A
23
18
51
52
53
54
55
56
58
59
60
61
62
64
65
66
70
72
73
74
75
76
79
80
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
D
10
D
11
D
12
D
13
D
14
D
15
Data
1
100
99
96
95
94
93
92
90
89
88
87
86
83
82
81
Control
ADS
BHE
BLE
BUSY
CLK2
D C
ERROR
FLT
HLDA
HOLD
INTR
LOCK
M IO
NA
NMI
PEREQ
READY
RESET
W R
16
19
17
34
15
24
36
28
3
4
40
26
23
6
38
37
7
33
25
N C
20
27
29
30
31
43
44
45
46
47
V
CC
8
9
10
21
32
39
42
48
57
69
71
84
91
97
V
SS
2
5
11
12
13
14
22
35
41
49
50
63
67
68
77
78
85
98
2
376 EMBEDDED PROCESSOR
Top View
(Component Side)
240182 –49
Bottom View
(Pin Side)
240182– 2
Figure 1 2 80376 88-Pin Grid Array Pin Out
3
376 EMBEDDED PROCESSOR
Table 1 2 88-Pin Grid Array Pin Assignments
Pin
2H
9B
8A
8B
7A
7B
6A
6B
5A
5B
4B
4A
3B
2D
1E
2E
1F
9A
10A
10B
12C
13D
Label
CLK2
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
23
A
22
A
21
A
20
A
19
Pin
12D
12E
13E
12F
13F
12G
13G
13H
12H
13J
12J
12K
13K
12L
12M
11M
10M
1K
2J
2K
4M
3M
Label
A
18
A
17
A
16
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
BLE
BHE
W R
D C
Pin
2L
5M
1J
1H
2G
1G
2F
7N
7M
8N
9M
8M
6M
2B
12B
1C
2M
3N
5N
10N
1A
3A
Label
M IO
LOCK
ADS
READY
NA
HOLD
HLDA
PEREQ
BUSY
ERROR
INTR
NMI
RESET
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
Pin
11A
13A
13C
13L
1N
13N
11B
2C
1D
1M
4N
9N
11N
2A
12A
1B
13B
13M
2N
6N
12N
1L
Label
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
N C
4
376 EMBEDDED PROCESSOR
The following table lists a brief description of each pin on the 80376 The following definitions are used in
these descriptions
I
O
I O
The named signal is active LOW
Input signal
Output signal
Input and Output signal
No electrical connection
Symbol
CLK2
RESET
Type
I
I
Name and Function
CLK2
provides the fundamental timing for the 80376 For additional
information see
Clock
in Section 4 1
RESET
suspends any operation in progress and places the 80376 in a
known reset state See
Interrupt Signals
in Section 4 1 for additional
information
DATA BUS
inputs data during memory I O and interrupt acknowledge
read cycles and outputs data during memory and I O write cycles See
Data Bus
in Section 4 1 for additional information
ADDRESS BUS
outputs physical memory or port I O addresses See
Address Bus
in Section 4 1 for additional information
WRITE READ
is a bus cycle definition pin that distinguishes write
cycles from read cycles See
Bus Cycle Definition Signals
in Section
4 1 for additional information
DATA CONTROL
is a bus cycle definition pin that distinguishes data
cycles either memory or I O from control cycles which are interrupt
acknowledge halt and instruction fetching See
Bus Cycle Definition
Signals
in Section 4 1 for additional information
MEMORY I O
is a bus cycle definition pin that distinguishes memory
cycles from input output cycles See
Bus Cycle Definition Signals
in
Section 4 1 for additional information
BUS LOCK
is a bus cycle definition pin that indicates that other
system bus masters are denied access to the system bus while it is
active See
Bus Cycle Definition Signals
in Section 4 1 for additional
information
ADDRESS STATUS
indicates that a valid bus cycle definition and
address (W R D C M IO BHE BLE and A
23
–A
1
) are being driven at
the 80376 pins See
Bus Control Signals
in Section 4 1 for additional
information
NEXT ADDRESS
is used to request address pipelining See
Bus
Control Signals
in Section 4 1 for additional information
BUS READY
terminates the bus cycle See
Bus Control Signals
in
Section 4 1 for additional information
BYTE ENABLES
indicate which data bytes of the data bus take part in
a bus cycle See
Address Bus
in Section 4 1 for additional
information
BUS HOLD REQUEST
input allows another bus master to request
control of the local bus See
Bus Arbitration Signals
in Section 4 1
for additional information
D
15
–D
0
I O
A
23
–A
1
W R
O
O
D C
O
M IO
O
LOCK
O
ADS
O
NA
READY
BHE BLE
I
I
O
HOLD
I
5
模拟电子
