NIS5452 Series
+5 Volt Electronic Fuse
The NIS5452 series is a cost effective, resettable fuse. It is designed
to buffer the load device from excessive input voltage which can
damage sensitive circuits. It also includes an overvoltage clamp circuit
that limits the output voltage during transients but does not shut the
unit down, thereby allowing the load circuit to continue operation.
Features
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•
•
•
•
•
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Integrated Power Device
33 mW Typical
Internal Charge Pump
Internal Undervoltage Lockout Circuit
Internal Overvoltage Clamp
These are Pb−Free Devices and are RoHS Compliant
5 AMP, 5 VOLT
ELECTRONIC FUSE
WDFN10
CASE 522AA
Typical Applications
•
Mother Board
•
Hard Drives
•
Fan Drives
MARKING DIAGRAM
1
XXX
AYWG
G
Pin
1−5
6
7
8
9
10
11 (flag)
Function
SOURCE
NC
ILIMIT
Enable/Fault
dv/dt
GND
VCC
XXX = Specific Device Code
A
= Assembly Location
Y
= Year
W = Work Week
= Pb−Free Package
G
(Note: Microdot may be in either location)
PIN ASSIGNMENTS
Src
Src
Src
Src
Src
(Top View)
GND
dv/dt
En/Flt
I
LIM
NC
ORDERING INFORMATION
Device
NIS5452MT1TXG
NIS5452MT1TWG
Features
Thermal Latching
V
clamp
= 5.85 V, I
LIM
= 2.1 A @ 18
W
Thermal Latching
V
clamp
= 5.85 V, I
LIM
= 2.1 A @ 18
W
Marking
52
52W
Package
WDFN10
(Pb−Free)
WDFN10
(Pb−Free)
Shipping
†
3000 / Tape & Reel
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2016
1
June, 2016 − Rev. 3
Publication Order Number:
NIS5452/D
NIS5452 Series
VIN
Enable
Enable/Fault
Charge
Pump
VOUT
Current
Limit
ILIMIT
Thermal
Shutdown
Voltage
Clamp
dv/dt
Control
dV/dt
UVLO
Figure 1. Block Diagram
FUNCTIONAL PIN DESCRIPTION
Pin
1−5
7
8
Function
Source
I
Limit
Enable/Fault
Description
GND
This pin is the source of the internal power FET and the output terminal of the fuse.
A resistor between this pin and the source pin sets the overload and short circuit current limit levels.
The enable/fault pin is a tri−state, bidirectional interface. It can be used to enable or disable the
output of the device by pulling it to ground using an open drain or open collector device. If a thermal
fault occurs, the voltage on this pin will go to an intermediate state to signal a monitoring circuit that
the device is in thermal shutdown. It can also be connected to another device in this family to cause
a simultaneous shutdown during thermal events.
The internal dv/dt circuit controls the slew rate of the output voltage at turn on. It has an internal ca-
pacitor that allows it to ramp up over a period of 1.4 ms. An external capacitor can be added to this
pin to increase the ramp time. If an additional time delay is not required, this pin should be left open.
Negative input voltage to the device. This is used as the internal reference for the IC.
Positive input voltage to the device.
9
dv/dt
10
11 (belly pad)
Ground
V
CC
MAXIMUM RATINGS
Rating
Input Voltage, operating, steady−state (V
CC
to GND, Note 1)
Thermal Resistance, Junction−to−Air
0.1 in
2
copper (Note 2)
0.5 in
2
copper (Note 2)
JESD51−7 4−layer board
Thermal Resistance, Junction−to−Lead (Pin 1)
Thermal Resistance, Junction−to−Case
Total Power Dissipation @ T
A
= 25°C (operating)
Operating Temperature Range (Notes 3 and 4)
Nonoperating Temperature Range
Lead Temperature, Soldering (10 Sec)
Symbol
V
IN
q
JA
Value
−0.6 to 14
154
93
50
49
20
2.5
−40 to 150
−55 to 155
260
°C/W
°C/W
W
°C
°C
°C
Unit
V
°C/W
q
JL
q
JC
P
max
T
J
T
J
T
L
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Negative voltage will not damage device provided that the power dissipation is limited to the rated allowable power for the device.
2. 1 oz copper, double−sided FR4.
3. Thermal limit is set above the maximum thermal rating. It is not recommended to operate this device at temperatures greater than the
maximum ratings for extended periods of time.
4. Exceeding T
J
will thermally destroy the FET. See AND9042/D.
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2
NIS5452 Series
ELECTRICAL CHARACTERISTICS
(Unless otherwise noted: V
CC
= 5.0 V, C
in
= 2.2
mF,
C
L
= 70
mF,
dv/dt pin open, T
A
= 25°C unless otherwise noted.)
Characteristics
POWER FET
Delay Time (enabling of chip to I
D
= 100 mA with 1 A resistive load) (Note 9)
ON Resistance (Note 5)
T
J
= 140°C (Note 6)
Off State Output Voltage
(V
CC
= 8 V
dc
, V
GS
= 0 V
dc
, R
L
= 100 kW) (Note 9)
Output Capacitance
(V
DS
= 5 V
DC
, V
GS
= 0 V
DC
, R
L
=
R)
Continuous Current (T
A
= 25°C, 0.5 in
2
pad) (Note 6)
(T
A
= 25°C, JESD51−7 4−layer board)
(T
A
= 80°C, minimum copper)
THERMAL LATCH
Shutdown Temperature (Note 6)
Thermal Hysteresis (Decrease in die temperature for turn on, does not apply
to latching parts)
UNDER/OVERVOLTAGE PROTECTION
V
OUT
Maximum (V
CC
= 8 V)
Undervoltage Lockout (Turn on, Voltage Going High)
UVLO Hysteresis (Note 9)
CURRENT LIMIT
Kelvin Short Circuit Current Limit (Note 7)
Direct Short Circuit Current Limit (Note 7)
Direct Overload Current Limit (Note 7)
dv/dt CIRCUIT
Output Voltage Ramp Time (Enable to V
OUT
= 4.7 V) (Note 9)
Maximum Capacitor Voltage
ENABLE/FAULT
Logic Level Low (Output Disabled)
Logic Level Mid (Thermal Fault, Output Disabled)
Logic Level High (Output Enabled) (Note 9)
High State Maximum Voltage
Logic Low Sink Current (V
enable
= 0 V)
Logic High Leakage Current for External Switch (V
enable
= 3.3 V)
Maximum Fanout for Fault Signal (Total number of chips that can be
connected to this pin for simultaneous shutdown)
TOTAL DEVICE
Bias Current (Operational) (Note 9)
Bias Current (Shutdown) (Note 9)
Minimum Operating Voltage (Notes 6 and 8)
I
Bias
I
Bias
V
min
400
100
2.8
750
mA
mA
V
V
in−low
V
in−mid
V
in−high
V
in−max
I
in−low
I
in−leak
Fan
0.35
0.82
1.96
2.51
0.58
1.4
2.2
3.3
−12
0.81
1.95
2.50
5.2
−20
1.0
3.0
V
V
V
V
mA
mA
Units
t
slew
V
max
0.70
1.4
2.4
V
CC
ms
V
NIS5452 (R
Limit
= 18
W)
NIS5452 (R
Limit
= 18
W)
NIS5452 (R
Limit
= 18
W)
I
LIM
I
LIM
I
LIM
1.6
2.1
2.0
7.2
2.8
A
A
A
NIS5452
V
out−clamp
V
UVLO
V
Hyst
5.5
2.2
5.85
2.5
0.145
6.25
2.8
V
V
V
T
SD
T
Hyst
150
175
45
200
°C
°C
T
dly
R
DS(on)
V
off
C
out
I
D
25
200
33
60
10
230
4.2
5.0
2.3
50
200
ms
mW
mV
pF
A
Symbol
Min
Typ
Max
Unit
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Pulse test: Pulse width 300
ms,
duty cycle 2%.
6. Verified by design.
7. Refer to explanation of short circuit and overload conditions in application note AND8140/D.
8. Device will shut down prior to reaching this level based on actual UVLO trip point.
9. Guaranteed by characterization or design.
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NIS5452 Series
+5V
11
VIN
5
VOUT
4
3
2
1
NIS5452
I Limit 7
R LIMIT
LOAD
8
Enable
Enable/Fault
GND
10
dV /dt
9
GND
Figure 2. Application Circuit with Direct Current Sensing
100
100
I
LIM(OL)
(A)
I
LIM
(A)
10
I
LIM(OL)
10
−40°C
125°C
25°C
I
LIM(SC)
1
5
10
15
20
25
30
R
LIMIT
(W)
1
5
10
15
20
25
30
R
LIMIT
(W)
Figure 3. Current Limit vs. R
Limit
for Direct
Sensing
100
Figure 4. Overload Current Limit vs. R
Limit
for
Direct Sensing and Ambient Temperature
I
LIM(SC)
(A)
10
−40°C
125°C
1
5
10
15
20
25
30
R
LIMIT
(W)
Figure 5. Short Circuit Current Limit vs. R
Limit
for Direct Sensing and Ambient Temperature
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4
NIS5452 Series
+5V
11
VIN
5
VOUT
4
3
2
1
7
R LIMIT
NIS5452
I Limit
LOAD
8
Enable
Enable/Fault
GND
10
dV /dt
9
GND
Figure 6. Application Circuit with Kelvin Current Sensing
100
100
I
LIM(OL)
(A)
I
LIM
(A)
10
I
LIM(OL)
−40°C
10
125°C
25°C
I
LIM(SC)
1
5
10
15
20
25
30
R
LIMIT
(W)
1
5
10
15
20
25
30
R
LIMIT
(W)
Figure 7. Current Limit vs. R
Limit
for Kelvin
Sensing
10
Figure 8. Overload Current Limit vs. R
Limit
for
Kelvin Sensing and Ambient Temperature
I
LIM(SC)
(A)
−40°C
125°C
1
5
10
15
20
25
30
KELVIN R
LIMIT
(W)
Figure 9. Short Circuit Current Limit vs. R
Limit
for Kelvin Sensing and Ambient Temperature
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