NJU26100 Series
NJU26100 Series Hardware Specification
■
General Description
This document describes the NJU26100 Series common hardware specifications.
This document is applied to the NJU26101 up to the NJU26199.
The individual function is described in the each data sheet. Please refer to the
each data sheet to find the detail functions. The firmware commands are
described in the each firmware document.
■
Package
■
Hardware Specification
NJU26100
Series
•
24bit Fixed-point Digital Signal Processing
•
Maximum System Clock Frequency
: 38MHz
•
Digital Audio Interface
: 3 Input ports / 3 Output ports
•
Master / Slave Mode
:1/2 fclk, 1/3 fclk
•
Master Mode MCK
ex. MCK = 384Fs(1/2) or MCK = 256Fs(1/3) at fclk=768Fs
•
Two kinds of micro computer interface
I
2
C bus (standard-mode/100kbps)
Serial interface (4 lines: clock, enable, input data, output data)
•
Power Supply
: 2.5V ( 3.3V Input tolerant )
•
Package
: QFP32-R1
AD1/SDIN
AD2/SSb
NJU26100 Series
DSP ARITHMETIC UNIT
SERIAL AUDIO
INTERFACE
BCKO
LRO
SERIAL OUT
24-BIT x 24-BIT
MULTIPLIER
ALU
SERIAL OUT
SERIAL OUT
SERIAL IN
SDO0
SDO1
SDO2
SDI0
SDI1
SDI2
BCKI
LRI
SCL/SCK
SDA/SDOUT
SERIAL
HOST
INTERFACE
PROGRAM
CONTROL
RESETb
MCK
XI
XO
TIMING
GENERATOR
ADDRESS GENERATION UNIT
SERIAL IN
SERIAL IN
DELAY
RAM
DATA
RAM
FIRMWARE
ROM
GPIO AND
CONFIGURATION
INTERFACE
GPIO0
GPIO1
Ver.2005-02-24
-1-
NJU26100 Series
■
Pin Configuration
VDDR
VDDR
VDDC
VDDC
VSSR
2 4
VSSR
2 3
VSSC
VSSC
2 2
2 1
2 0
1 9
1 8
1 7
SDI0
SDI1
SDI2
LRI
BCKI
MCK
BCKO
LRO
25
GPIO1
VSSC
VDDC
RESETb
VSSO
XO
XI
VDDO
16
26
15
27
14
NJU26100
Series
28
29
30
31
32
1
13
12
11
10
9
2
3
4
5
6
7
8
SDO2
SDO1
SDO0
GPIO0
SCL/SCK
SDA/SDOUT
AD1/SDIN
AD2/SSb
■
Pin Description
Pin Description
No. Symbol
I/O Description
No. Symbol I/O Description
1
SDO2
O
Audio Data Output CH2
17
VDDC
--
Core Power Supply +2.5V
2
SDO1
O
Audio Data Output CH1
18
VDDC
--
Core Power Supply +2.5V
3
SDO0
O
Audio Data Output CH0
19
VSSC
--
Core GND
4
GPIO0
I/O General Purpose IO
20
VSSC
--
Core GND
2
5
SCL/SCK
I
I C Clock / Serial Clock
21
VDDR
--
I/O Power Supply +2.5V
2
6
SDA/SDOUT
I/O I C I/O / Serial Output
22
VDDR
--
I/O Power Supply +2.5V
2
7
AD1/SDIN
I
I C Address / Serial Input
23
VSSR
--
I/O GND
2
8
AD2/SSb
I
I C Address / Serial Enable
24
VSSR
--
I/O GND
9
VDDO
--
OSC Power Supply +2.5V
25
SDI0
I
Audio Data Input CH0
10
XI
I
X’tal Clock Input
26
SDI1
I
Audio Data Input CH1
11
XO
O
OSC Output
27
SDI2
I
Audio Data Input CH2
12
VSSO
--
OSC GND
28
LRI
I
LR Clock Input
13
RESETb
I
RESET (active Low)
29
BCKI
I
Bit Clock Input
14
VDDC
--
Core Power Supply +2.5V
30
MCK
O
Master Clock Output
15
VSSC
--
Core GND
31
BCKO
O
Bit Clock Output
16
GPIO1
I/O General Purpose IO
32
LRO
O
LR Clock Output
*1 I : Input, O : Output, I/O : Bi-directional
*2 SDI0, SDI1, SDI2, SDO0, SDO1, SDO2, GPIO0, GPIO1 are different by any function. Refer to each datasheet.
-2-
Ver.2005-02-24
NJU26100 Series
1. Electric Characteristics
1.1 Absolute Maximum Ratings
Table1-1 Absolute Maximum Ratings
(V
SSO
=V
SSC
=V
SSR
=0V, Ta=25°C)
Parameter
Supply Voltage
XI Input Voltage
Input Pin Voltage
Symbol
V
DD
V
x(OSC)
V
x(IN)
Rating
0 to 3.05
-0.3 to V
DD
-0.3 to 3.6
Units
V
V
V
Power Dissipation
P
D
0.3
W
Storage Temperature
T
stg
-40 to +125
°C
1
* They apply SCL/SCK, AD1/SDIN, AD2/SSb, RESETb, SDI0, SDI1, SDI2, LRI, and BCKI pin. It applies to GPIO0
(SEL1) pin of NJU26100 series except NJU26150. However, it applies to SDA/SDOUT pin at the time of I
2
C
mode operation.
Ver.2005-02-24
-3-
NJU26100 Series
1.2 Electric Characteristics
Table1-2 Electric Characteristics
(V
DDO
=V
DDC
=V
DDR
=2.5V, V
SSO
=V
SSC
=V
SSR
=0V, Ta=25°C)
Parameter
Operating V
DD
Voltage
Operating Current
Operating Temperature
Recommended Operating
Temperature
High Level Input
Voltage (XI)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
High Level Input Current
Low Level Input Current
High Level Output Voltage
Low Level Output Voltage
Input Capacitance
Input Rise/Fall transition Time
Clock Frequency
Ext.System Clock Duty Cycle
Symbol
V
DD
I
DD
T
OPR
T
OPRR
V
IH(OSC)
V
IH
V
IL
I
IH
I
IH(pd)
I
IL
V
OH
V
OL
C
IN
t
r
/ t
f
f
OSC
r
EC
except for SCL/SCK,
SDA/SDOUT,
AD1/SDIN, AD2/SS½
pin*
1
XI pin
XI pin
V
SS
=V
SSO
=V
SSC
=V
SSR
V
IN
=3.3V
expect for GPIO pin
V
IN
=3.3V
GPIO pin Only
V
IN
=V
SSO
=V
SSC
=V
SSR
I
OH
=-2mA
I
OH
=-100µA
I
OL
=2mA
V
DDO
=V
DDC
=V
DDR
=2.5V
XI pin
Test Condition
V
DDO
, V
DDC
, V
DDR
pin
f
OSC
=36.864MHz
Min.
2.25
-
-40
-10
2.0
2.0
V
SS
-10
100
-10
V
DD
-0.4
V
DD
-0.1
-
-
-
-
47.5
Typ.
2.5
40
25
25
-
-
-
-
-
-
-
-
5
-
-
50
Max.
2.75
-
85
70
V
DD
3.3
0.5
+10
300
+10
-
0.4
-
100
38.0
52.5
Units
V
mA
°C
°C
V
V
V
µA
µA
µA
V
V
pF
ns
MHz
%
*
1
The tr / tf of these pins are specified separately.
*
2
All input / input-and-output pins serve as the Schmidt trigger input except for XI pin.
V
DDR
Input
pin
VDDC
Output
pin
V
DDR
XI
V
SSR
pin
XI / XO pin
(XI, XO)
V
SSC
Input pin
(GPIO0, SCL/SCK, SDA/SDOUT,
AD1/SDIN, AD2/SSb, RESETb, GPIO1,
SDI0, SDI1, SDI2, LRI, BCKI pin)
V
DDC
V
DDO
XO
pin
V
SSO
V
SSC
Output pin
(SDO0, SDO1, SDO2, GPIO0,
*
3
SDA/SDOUT, GPIO1, MCK,
BCKO, LRO pin)
Fig.1- 1 I/O Equivalent Circuits
*
3
SDA becomes Open-Drain at the time of the output of I
2
C.
-4-
Ver.2005-02-24
NJU26100 Series
2. Clock and Reset
The NJU26100 Series XI pin requires the system clock that should be related to the sample frequency Fs. The
XI/XO pins can generate the system clock by connecting the crystal oscillator or the ceramic resonator.
When the external oscillator is connected to XI/XO pins, check the voltage level of the pins. Because the
maximum input voltage level of XI pin is deferent from the other input or bi-directional pins. The maximum
voltage-level of XI pin equals to V
DD
.
To initialize the NJU26100 Series, RESETb pin should be set Low level during some period. After some period of
Low level, RESETb pin should be High level. This procedure starts the initialization of the NJU26100 Series.
To select I
2
C bus or 4-Wire serial bus, some level should be supplied to GPIO0 pin (SEL1 pin). When GPIO0 pin
(SEL1 pin)=”Low”, I
2
C bus is selected. When GPIO0 pin (SEL1 pin)=”High”, 4-Wire serial bus is selected. The level
of GPIO0 pin (SEL1 pin) is checked by the NJU26100 Series in 1 m sec after RESETb pin level goes to “High”.
After the power supply and the oscillation of the NJU26100 Series becomes stable, RESETb pin should be kept
Low-level more than t
RESETb
period.
V
DD
XI
OSC unstable
OSC stable
t
RESETb
RESETb
Fig. 2- 1 Reset Timing
Table 2- 1 Reset Time
Symbol
t
RESETb
Time
≥1µs
Notice :
Please consult with manufacture of crystal oscillator / ceramic resonator enough in use of these parts.
NJRC would not take the responsibility on the external parts of clock generating.
Ver.2005-02-24
-5-
FPGA/CPLD
