NJU26120
■
General Description
Digital Signal Processor for TV
■
Package
The NJU26120 is a high performance 24-bit digital signal processor.
The NJU26120 provides ‘Lip
sync Audio Delay’,
‘eala’, ‘ealaBass’, 7band PEQ,
Tone Control, Clipper, Headphone Surround and Continuous Signal Detector.
These kinds of sound functions are suitable for TV, mini-component, CD
radio-cassette, speakers system and other audio products.
■
FEATURES
NJU26120VC2
- Software
•
3D sound :
eala (NJRC Original Surround)
•
Sound Enhancement: :
ealaBASS (NJRC Original Dynamic Bass Boost)
•
Headphone Surround
•
7Band PEQ
•
Tone Control
•
Delay for Lip sync Audio Delay
( fs=48kHz : Max. 74msec, fs=44.1kHz : Max. 81msec, fs=32kHz : Max. 111msec )
•
Clipper
•
Master Volume
•
WatchDog Clock Output
- Hardware
•
24bit Fixed-point Digital Signal Processing
•
Maximum System Clock Frequency : 12.288MHz Max. built-in PLL Circuit
•
Digital Audio Interface
: 3 Input ports / 3 Output ports
•
Digital Audio Format
: I
2
S 24bit, Left- justified, Right-justified, BCK : 32/64fs
•
Master / Slave Mode
- Master Mode , MCK : 384fs @32kHz, 256fs @48kHz
•
Host Interface
: I
2
C bus (Fast-mode/400kbps)
•
Power Supply
: 3.3V
•
Input terminal
: 5V Input tolerant
•
Package
: SSOP24 –C2 (Pb-Free)
Ver.2008-12-01
-1-
NJU26120
■
Function Block Diagram
SCL
I C INTERFACE
SDA
PROGRAM
CONTROL
24Bit x 24Bit
MULTIPLIER
ALU
TIMING
GENERATOR /
PLL
ADDRESS GENERATION UNIT
SERIAL AUDIO
INTERFACE
SDO0-2
BCK
LR
2
24Bit Fixed-point DSP Core
SDI0-2
RESETb
MCK
CLKOUT
CLK
SLAVEb
Internal Pow er
(1.8V)
WDC
FIRMWARE
ROM
GPIO
INTERFACE
PROC
AD1
Built-in LDO
VREGO
External
Low -ESR
Capacitors
Required
DATA RAM
1.8V level terminal
Fig. 1 NJU26120 Block Diagram
-2-
Ver.2008-12-01
NJU26120
■
DSP Block Diagram
mute
SDI0
SW1
SDI0
SDI1
SDI2
SW2
Trim
Pre1
Delay
Delay
Source
Trim
SDI0
SDI1
SDI2
Pre0
Select
Pre0
SDI1
SW3
SDI2
Trim
eala / eala D
eala Bass / eala Bass D
Tone/Bass
7Band
PEQ
HPF +
6PEQ
L/R Vol.
L/R Bal.
Master Vol.
Clipper
Continuous
Signal Detector
HPout
Pre2
all thru
Pre0
Pre1
Pre2
Headphone
Surround
To Microcomputer
WDC
System Monitor
WDC Clock Generator
HPout
SDO0
SDO1
Serial Audio
Outputs
SDO2
Fig. 2 NJU26120 Function Diagram
Ver.2008-12-01
-3-
NJU26120
■
Pin Configuration
RESETb
LR
BCK
SDI2
SDI1
SDI0
MCK
VDD
VSS
STBYb
VSS
VREGO
1
2
3
4
5
6
7
8
9
10
11
12
NJU26120
24
23
22
21
20
19
18
17
16
15
14
13
TEST
SCL
SDA
SDO2
SDO1
SDO0
WDC
PROC
AD1
SLAVEb
CLK
CLKOUT
SSOP24-C2
Fig. 3 NJU26120 Pin Configuration
■
Pin Description
Table 1 Pin Description
No. Symbol
I/O Description
No. Symbol
I/O Description
1
RESETb I
RESET (active Low)
13
CLKOUT
O
OSC Output
2
LR
I/O LR Clock
14
CLK
I
OSC Clock Input
3
BCK
I/O Bit Clock
15
SLAVEb
I
Slave select
4
SDI2
I
Audio Data Input 2 L/R
16
AD1
I
I
2
C Address
5
SDI1
I
Audio Data Input 1 L/R
17
PROC
I
Status select after Reset DSP
6
SDI0
I
Audio Data Input 0 L/R
18
WDC
OD Clock for Watch Dog Timer
7
MCK
I/O Master Clock
19
SDO0
O
Audio Data Output 0 L/R
8
VDD
-
Power Supply +3.3V
20
SDO1
O
Audio Data Output 1 L/R
9
VSS
-
GND
21
SDO2
O
Audio Data Output 2 L/R
10
STBYb
I
For TEST (Connected to VDD)
22
SDA
OD I
2
C I/O
11
VSS
-
GND
23
SCL
I
I
2
C Clock
12
VREGO PI
Built-in Power Supply Bypass
24
TEST
I
For TEST(Connected to VSS)
* I : Input, O : Output, I/O: Bi-directional, OD: Open-Drain I/O, PI: Power Supply Bypass
AD1 (No.16) pin and PROC (No.17) pin are input pins. WDC (No.18) pin is open-drain pin with pull-up resistance.
However, these pins operate as bi-directional pins. No.11pin and No.12pin connect with V
DD
or V
SS
through 3.3kΩ
resistance. No.18pin do not connect or connect with V
DD
through 3.3kΩ resistance when unused.
VREGO (No.12) pin is a built-in power supply bypass pin. Connect low-ESR capacitor of 4.7uF and 0.01uF in parallel
between VSS (No.11) pin. A built-in power supply is used only for NJU26120 operation. Be not short-circuited of this pin.
Do not take out the current, and connect other power supplies.
-4-
Ver.2008-12-01
NJU26120
■
Absolute Maximum Ratings
( V
SS
=0V=GND, Ta=25°C )
°
Rating
Units
Table 2 Absolute Maximum Ratings
Parameter
Symbol
Supply Voltage *
Supply Voltage Bypass *
In
I/O, OD
Pin Voltage *
Out
CLK
CLKOUT
Power Dissipation
Operating Voltage
Storage Temperature
V
DD
V
REGO
V
x(IN)
V
x(I/O)
,V
x(OD)
V
x(OUT)
V
x(CLK)
V
x(CLKOUT)
-0.3 to 3.8
-0.3 to 2.1
-0.3 to 5.5 (V
DD
≥
3.0V)
-0.3 to 3.8 (V
DD
< 3.0V)
-0.3 to 3.8
-0.3 to 3.8
V
V
V
300
mW
P
D
-10 to 85
T
OPR
°C
T
STR
-40 to 125
°C
* The LSI must be used inside of the “Absolute maximum ratings”. Otherwise, a stress may cause permanent
damage to the LSI.
* V
DD
: 8 pin
* V
REGO
: 12 pin
* V
x(IN)
: 1, 4, 5, 6, 10, 15, 16, 17, 23, 24 pin
* V
x(OD)
: 18, 22 pin
* V
x(I/O)
: 2, 3, 7 pin
* V
x(OUT)
: 19, 20, 21 pin
* V
x(CLK)
: 14 pin
* V
x(CLKOUT)
: 13 pin
V
DD
V
DD
(1.8V)
V
DD
V
DD
(1.8V)
■
Terminal equivalent circuit diagram
PAD
R
PD
Input, I/O (Input part)
(1 to 7, 22, 23pin)
(With R
PD
: 15, 16, 17, 24pin)
CLK
CLKOUT
V
SS
CLK/CLKOUT
(13, 14pin)
V
SS
V
DD
R
PU
PAD
Output Disable
PAD
V
DD
Output, I/O (Output part)
(2, 3, 7, 19, 20, 21pin )
( Open Drain Output with R
PU
: 18pin)
( Open Drain Output: 22pin )
V
SS
V
SS
STBYb
(10pin)
Fig.4 NJU26120 Terminal equivalent circuit diagram
Ver.2008-12-01
-5-
