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NL27WZ08US

Logic Gates 1.65-5.5V Dual

器件类别:逻辑    逻辑   

厂商名称:ON Semiconductor(安森美)

厂商官网:http://www.onsemi.cn

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器件参数
参数名称
属性值
是否Rohs认证
不符合
厂商名称
ON Semiconductor(安森美)
零件包装代码
SOIC
包装说明
VSSOP, TSSOP8,.12,20
针数
8
Reach Compliance Code
not_compliant
ECCN代码
EAR99
Factory Lead Time
1 week
系列
27WZ
JESD-30 代码
R-PDSO-G8
JESD-609代码
e0
长度
2.3 mm
负载电容(CL)
50 pF
逻辑集成电路类型
AND GATE
最大I(ol)
0.024 A
湿度敏感等级
1
功能数量
2
输入次数
2
端子数量
8
最高工作温度
85 °C
最低工作温度
-40 °C
封装主体材料
PLASTIC/EPOXY
封装代码
VSSOP
封装等效代码
TSSOP8,.12,20
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH
包装方法
TAPE AND REEL
峰值回流温度(摄氏度)
240
电源
3.3 V
Prop。Delay @ Nom-Sup
5.2 ns
传播延迟(tpd)
11 ns
认证状态
Not Qualified
施密特触发器
NO
座面最大高度
0.9 mm
最大供电电压 (Vsup)
5.5 V
最小供电电压 (Vsup)
1.65 V
标称供电电压 (Vsup)
1.8 V
表面贴装
YES
技术
CMOS
温度等级
INDUSTRIAL
端子面层
Tin/Lead (Sn/Pb)
端子形式
GULL WING
端子节距
0.5 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
30
宽度
2 mm
文档预览
NL27WZ08
Dual 2-Input AND Gate
The NL27WZ08 is a high performance dual 2−input AND Gate
operating from a 1.65 V to 5.5 V supply.
Features
Extremely High Speed: t
PD
2.5 ns (typical) at V
CC
= 5 V
Designed for 1.65 V to 5.5 V V
CC
Operation
Over Voltage Tolerant Inputs
LVTTL Compatible
Interface Capability With 5 V TTL Logic with
V
CC
= 3 V
LVCMOS Compatible
24 mA Balanced Output Sink and Source Capability
Near Zero Static Supply Current Substantially Reduces System
Power Requirements
Replacement for NC7WZ08
Chip Complexity: FET = 124
These Devices are Pb−Free and are RoHS Compliant
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
http://onsemi.com
MARKING
DIAGRAM
8
1
US8
US SUFFIX
CASE 493
1
L2
M
G
= Device Code
= Date Code*
= Pb−Free Package
8
L2 M
G
G
(Note: Microdot may be in either location)
*Date Code orientation may vary depending upon
manufacturing location.
A1
1
8
V
CC
PIN ASSIGNMENT
Pin
1
2
3
4
Function
A1
B1
Y2
GND
A2
B2
Y1
V
CC
B1
2
7
Y1
Y2
3
6
B2
5
6
7
8
GND
4
5
A2
FUNCTION TABLE
Figure 1. Pinout
Inputs
A
IEEE/IEC
A1
B1
A2
B2
&
Y1
Y2
L
L
H
H
H = HIGH Logic Level
L = LOW Logic Level
B
L
H
L
H
Y = AB
Output
Y
L
L
L
H
Figure 2. Logic Symbol
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
©
Semiconductor Components Industries, LLC, 2012
April, 2012
Rev. 10
1
Publication Order Number:
NL27WZ08/D
NL27WZ08
MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
T
L
T
J
q
JA
P
D
MSL
F
R
V
ESD
DC Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
V
I
< GND
DC Output Diode Current
V
O
< GND
DC Output Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature under Bias
Thermal Resistance (Note 1)
Power Dissipation in Still Air at 85°C
Moisture Sensitivity
Flammability Rating
Oxygen Index: 28 to 34
ESD Withstand Voltage
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
Latch−Up Performance
Above V
CC
and Below GND at 85°C (Note 5)
Parameter
Value
−0.5
to +7.0
−0.5
to +7.0
−0.5
to V
CC
+ 0.5
−50
−50
±50
±100
±100
−65
to +150
260
+150
250
250
Level 1
UL 94 V−0 @ 0.125 in
> 2000
> 200
N/A
±500
V
Units
V
V
V
mA
mA
mA
mA
mA
°C
°C
°C
°C/W
mW
I
Latch−Up
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
Supply Voltage
Operating
Data Retention Only
Input Voltage (Note 6)
Output Voltage (HIGH or LOW State)
Operating Free−Air Temperature
Input Transition Rise or Fall Rate
V
CC
= 2.5 V
±0.2
V
V
CC
= 3.0 V
±0.3
V
V
CC
= 5.0 V
±0.5
V
Parameter
Min
1.65
1.5
0
0
−55
0
0
0
Max
5.5
5.5
5.5
5.5
+125
20
10
5
Units
V
V
I
V
O
T
A
Dt/DV
V
V
°C
ns/V
6. Unused inputs may not be left open. All inputs must be tied to a high− or low−logic input voltage level.
http://onsemi.com
2
NL27WZ08
DC ELECTRICAL CHARACTERISTICS
Symbol
V
IH
V
IL
V
OH
Parameter
High−Level Input Voltage
Low−Level Input Voltage
High−Level Output
Voltage
V
IN
= V
IL
or V
IH
I
OH
= 100
mA
I
OH
=
−3
mA
I
OH
=
−8
mA
I
OH
=
−12
mA
I
OH
=
−16
mA
I
OH
=
−24
mA
I
OH
=
−32
mA
I
OL
= 100
mA
I
OL
= 3 mA
I
OL
= 8 mA
I
OL
= 12 mA
I
OL
= 16 mA
I
OL
= 24 mA
I
OL
= 32 mA
V
IN
= 5.5 V or
GND
V
IN
= 5.5 V or
GND
V
IN
= 5.5 V or
V
OUT
= 5.5 V
Condition
V
CC
(V)
1.65
2.3 to 5.5
1.65
2.3 to 5.5
1.65 to 5.5
165
2.3
2.7
3.0
3.0
4.5
1.65 to 5.5
2.3
2.7
3.0
3.0
4.5
0 to 5.5
5.5
0
V
CC
0.1
1.29
1.9
2.2
2.4
2.3
3.8
V
CC
1.5
2.1
2.4
2.7
2.5
4.0
0.08
0.20
0.22
0.28
0.38
0.42
0.1
0.24
0.3
0.4
0.4
0.55
0.55
±0.1
1.0
1.0
T
A
= 255C
Min
0.75 V
CC
0.7 V
CC
0.25 V
CC
0.3 V
CC
V
CC
0.1
1.5
1.9
2.2
2.4
2.3
3.8
0.1
0.24
0.3
0.4
0.4
0.55
0.55
±1.0
10
10
Typ
Max
−555C
3
T
A
3
1255C
Min
0.75 V
CC
0.7 V
CC
0.25
0.3 V
CC
Max
Units
V
V
V
V
OL
Low−Level Output Voltage
V
IN
= V
IH
or V
OH
V
I
IN
I
CC
I
OFF
Input Leakage Current
Quiescent Supply Current
Power Off Leakage
Current
mA
mA
mA
AC ELECTRICAL CHARACTERISTICS
t
R
= t
F
= 3.0 ns
V
CC
Symbol
t
PLH
t
PHL
Parameter
Propagation Delay
(Figure 3 and 4)
Condition
R
L
= 1 MW, C
L
= 15 pF
R
L
= 1 MW, C
L
= 15 pF
R
L
= 500
W,
C
L
= 50 pF
R
L
= 1 MW, C
L
= 15 pF
R
L
= 500
W,
C
L
= 50 pF
(V)
1.8
±
0.15
2.5
±
0.2
3.3
±
0.3
5.0
±
0.5
Min
2.0
1.0
0.8
1.2
0.5
0.8
T
A
= 255C
Typ
5.7
3.5
2.6
3.2
1.9
2.5
Max
10.5
5.8
3.9
4.8
3.1
3.7
−555C
3
T
A
3
1255C
Min
2.0
2.0
0.8
1.2
0.5
0.8
Max
11.0
6.2
4.3
5.2
3.3
4.0
Units
ns
CAPACITIVE CHARACTERISTICS
Symbol
C
IN
C
PD
Input Capacitance
Power Dissipation Capacitance
(Note 7)
Parameter
Condition
V
CC
= 5.5 V, V
I
= 0 V or V
CC
10 MHz, V
CC
= 3.3 V, V
I
= 0 V or V
CC
10 MHz, V
CC
= 5.5 V, V
I
= 0 V or V
CC
Typical
4
25
30
Units
pF
pF
7. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD

V
CC

f
in
+ I
CC
. C
PD
is used to determine the no−load dynamic
power consumption; P
D
= C
PD

V
CC2

f
in
+ I
CC

V
CC
.
http://onsemi.com
3
NL27WZ08
t
f
= 3 ns
90%
50%
10%
90%
50%
10%
t
f
= 3 ns
V
CC
V
CC
INPUT
A and B
GND
R
L
V
OH
C
L
t
PHL
t
PLH
OUTPUT Y
50%
50%
V
OL
A 1−MHz square input wave is recommended for
propagation delay tests.
Figure 3. Switching Waveform
Figure 4. Test Circuit
DEVICE ORDERING INFORMATION
Device Order Number
NL27WZ08USG
NLV27WZ08USG*
Package Type
US8
(Pb−Free)
US8
(Pb−Free)
Shipping
3000 / Tape & Reel
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
http://onsemi.com
4
NL27WZ08
PACKAGE DIMENSIONS
US8
US SUFFIX
CASE 493−02
ISSUE B
J
A
8
5
−X−
−Y−
DETAIL E
B
L
1
4
R
P
G
S
U
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION “A” DOES NOT INCLUDE MOLD
FLASH, PROTRUSION OR GATE BURR.
MOLD FLASH. PROTRUSION AND GATE
BURR SHALL NOT EXCEED 0.140 MM
(0.0055”) PER SIDE.
4. DIMENSION “B” DOES NOT INCLUDE
INTER−LEAD FLASH OR PROTRUSION.
INTER−LEAD FLASH AND PROTRUSION
SHALL NOT E3XCEED 0.140 (0.0055”) PER
SIDE.
5. LEAD FINISH IS SOLDER PLATING WITH
THICKNESS OF 0.0076−0.0203 MM.
(300−800 “).
6. ALL TOLERANCE UNLESS OTHERWISE
SPECIFIED
±0.0508
(0.0002 “).
DIM
A
B
C
D
F
G
H
J
K
L
M
N
P
R
S
U
V
MILLIMETERS
MIN
MAX
1.90
2.10
2.20
2.40
0.60
0.90
0.17
0.25
0.20
0.35
0.50 BSC
0.40 REF
0.10
0.18
0.00
0.10
3.00
3.20
0
_
6
_
5
_
10
_
0.23
0.34
0.23
0.33
0.37
0.47
0.60
0.80
0.12 BSC
INCHES
MIN
MAX
0.075
0.083
0.087
0.094
0.024
0.035
0.007
0.010
0.008
0.014
0.020 BSC
0.016 REF
0.004
0.007
0.000
0.004
0.118
0.126
0
_
6
_
5
_
10
_
0.010
0.013
0.009
0.013
0.015
0.019
0.024
0.031
0.005 BSC
C
−T−
SEATING
PLANE
H
0.10 (0.004) T
N
R 0.10 TYP
V
D
0.10 (0.004)
K
M
T X Y
M
DETAIL E
F
SOLDERING FOOTPRINT*
3.8
0.15
0.50
0.0197
1.8
0.07
0.30
0.012
1.0
0.0394
SCALE 8:1
mm
inches
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor
and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone:
303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax:
303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email:
orderlit@onsemi.com
N. American Technical Support:
800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
ON Semiconductor Website: www.onsemi.com
Order Literature:
http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
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5
NL27WZ08/D
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