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NLV18HC1GT34DFT2G

Majority Logic Gate

器件类别:逻辑    逻辑   

厂商名称:ON Semiconductor(安森美)

厂商官网:http://www.onsemi.cn

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器件参数
参数名称
属性值
Reach Compliance Code
compliant
Is Samacsys
N
逻辑集成电路类型
MAJORITY LOGIC GATE
Base Number Matches
1
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NLV18HC1Gxx,
NLV18HC1GTxx
Automotive High Speed
Logic Gates
The NLV18HC1Gxx and NLV18HC1GTxx are automotive−grade
High−Speed CMOS logic gates.
The NLV18HC1Gxx devices have CMOS input voltage levels
while the NLV18HC1GTxx devices have TTL input voltage levels.
Features
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High Speed: t
PD
= 7 ns (Typ) at V
CC
= 6 V
Low Power Dissipation: I
CC
= 1
mA
(Max) at T
A
= 25°C
High Noise Immunity
Balanced Propagation Delays (t
PLH
= t
PHL
)
Symmetrical Output Impedance (I
OH
= I
OL
= 2 mA)
Operating Temperature:
−55°C
to +125°C
AEC Grade 1−Compliant:
−40°C
to +125°C
Tiny SC−88A Package (other package offerings may be available
upon request)
AEC−Q100 Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and RoHS
Compliant
FUNCTION LIST
xx
00
02
04
05
07
08
14
17
32
34
86
125
126
U04
2−Input NAND
2−Input NOR
Inverter
Open−Drain Inverter
Open−Drain Buffer
2−Input AND
Schmitt−Trigger Inverter
Schmitt−Trigger Buffer
2−Input OR
Buffer
2−Input XOR
Tri−State Buffer
Tri−State Buffer
Unbuffered Inverter
Function
MARKING
DIAGRAM
5
SC−88A
DF SUFFIX
CASE 419A
XX
M
G
XX MG
G
M
1
= Device Code
= Date Code*
= Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may vary
depending upon manufacturing location.
ORDERING INFORMATION
See detailed ordering and shipping information on page 10 of
this data sheet.
©
Semiconductor Components Industries, LLC, 2019
February, 2019
Rev. 0
1
Publication Order Number:
NLV18HC1G00/D
NLV18HC1Gxx, NLV18HC1GTxx
Functions and Function Tables – Buffers and Inverters
A
Y
A
Y
04
Inverter
U04
Unbuffered Inverter
A
0
1
Y
A
A
Y
1
0
A
0
1
34
Buffer
Y
0
1
Y
05
Open−Drain Inverter
A
0
1
Y
Hi−Z
0
A
0
1
07
Open−Drain Buffer
Y
0
Hi−Z
A
Y
A
Y
14
Schmitt−Trigger Inverter
A
0
1
Y
1
0
A
0
1
17
Schmitt−Trigger Buffer
Y
0
1
Pin Assignment
N.C.
1
5
V
CC
A
2
GND
3
4
Y
Pinout (Buffers and Inverters)
Pin
1
2
3
4
5
Name
N.C.
A
GND
Y
V
CC
Description
No Connection
Input
Ground
Output
Supply
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2
NLV18HC1Gxx, NLV18HC1GTxx
Functions and Function Tables – Tri−State Buffers and Bus Drivers
OE
OE
A
Y
A
Y
125
Tri−State Buffer
OE
0
0
1
X = Don’t Care
A
0
1
X
Y
0
1
Hi−Z
OE
0
1
1
X = Don’t Care
126
Tri−State Buffer
A
X
0
1
Y
Hi−Z
0
1
Pin Assignments
OE
1
5
V
CC
OE
1
5
V
CC
A
2
A
2
GND
3
4
Y
GND
3
4
Y
Pinout (125)
Pin
1
2
3
4
5
Name
OE
A
GND
Y
V
CC
Description
Enable (Active−Low)
Input
Ground
Output
Supply
Pin
1
2
3
4
5
Pinout (126)
Name
OE
A
GND
Y
V
CC
Description
Enable (Active−High)
Input
Ground
Output
Supply
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3
NLV18HC1Gxx, NLV18HC1GTxx
Functions and Function Tables
Gates
A
B
00
NAND
A
0
0
1
1
B
0
1
0
1
Y
1
1
1
0
A
0
0
1
1
A
B
08
AND
B
0
1
0
1
Y
0
0
0
1
Y
Y
A
B
02
NOR
A
0
0
1
1
B
0
1
0
1
Y
A
B
32
OR
Y
1
0
0
0
A
0
0
1
1
B
0
1
0
1
Y
Y
0
1
1
1
Pin Assignment
A
B
86
XOR
A
0
0
1
1
B
0
1
0
1
Y
0
1
1
0
Pin
1
2
3
4
5
Pinout (Gates)
Name
B
A
GND
Y
V
CC
Input
Input
Ground
Output
Supply
Description
GND
3
4
Y
A
2
Y
B
1
5
V
CC
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4
NLV18HC1Gxx, NLV18HC1GTxx
Table 1. MAXIMUM RATINGS
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
OUT
I
CC or
I
GND
T
STG
T
L
T
J
q
JA
P
D
MSL
F
R
V
ESD
I
LATCHUP
DC Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Source/Sink Current
DC Supply Current Per Supply Pin or Ground Pin
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Thermal Resistance (Note 1)
Power Dissipation in Still Air at 85°C
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage (Note 2)
Latchup Performance (Note 3)
Oxygen Index: 28 to 34
Human Body Model
Charged Device Model
Parameter
Value
−0.5
to +6.5
−0.5
to V
CC
+0.5
−0.5
to V
CC
+0.5
±20
±20
±12.5
±25
−65
to +150
260
+150
659
190
Level 1
UL 94 V−0 @ 0.125 in
2000
1000
±100
V
mA
Unit
V
V
V
mA
mA
mA
mA
°C
°C
°C
°C/W
mW
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 20 ounce copper trace with no air flow.
2. HBM tested to EIA / JESD22−A114−A. CDM tested to JESD22−C101−A. JEDEC recommends that ESD qualification to EIA/JESD22−A115A
(Machine Model) be discontinued.
3. Tested to EIA/JESD78 Class II.
Table 2. RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
V
OUT
T
A
t
r
, t
f
Positive DC Supply Voltage
Parameter
NLV18HC1Gxx
NLV18HC1GTxx
Digital Input Voltage
Output Voltage
Operating Free−Air Temperature
Input Transition Rise or Fall Rate
Functions 14 and 17
All Other Functions
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 3.0 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
0
0
0
0
0
No Limit
20
20
10
5
Min
2.0
4.5
0
0
−55
Max
6.0
5.5
V
CC
V
CC
+125
V
V
°C
ns/V
Unit
V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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5
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参数对比
与NLV18HC1GT34DFT2G相近的元器件有:NLV18HC1GT17DFT2G、NLV18HC1G17DFT2G。描述及对比如下:
型号 NLV18HC1GT34DFT2G NLV18HC1GT17DFT2G NLV18HC1G17DFT2G
描述 Majority Logic Gate Majority Logic Gate Majority Logic Gate
Reach Compliance Code compliant compliant compli
逻辑集成电路类型 MAJORITY LOGIC GATE MAJORITY LOGIC GATE BUFFER
Is Samacsys N N -
Base Number Matches 1 1 -
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