Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27C128 pins.
Commercial Temp. Range
(0˚C to +70˚C) V
CC
= 5V
±
10%
Parameter/Order Number
NM27C128 Q, N, V 90
NM27C128 Q, N, V 120
NM27C128 Q, N, V 150
NM27C128 Q, N, V 200
Access Time (ns)
90
120
150
200
Extended Temp. Range
(−40˚C to +85˚C) V
CC
= 5V
±
10%
Parameter/Order Number
NM27C128 QE, NE, VE 120
NM27C128 QE, NE, VE 150
NM27C128 QE, NE, VE 200
Access Time (ns)
120
150
200
Note:
Surface mount PLCC package available for commercial and extended
temperature ranges only.
Pin Names
Symbol
A0–A13
CE
OE
O0–O7
PGM
NC
Description
Addresses
Chip Enable
Output Enable
Outputs
Program
No Connect
Package Types: NM27C128 Q, N, V XXX
Q = Quartz-Windowed Ceramic DIP
N = Plastic OTP DIP
V = Surface-Mount PLCC
•
All packages conform to the JEDEC standard.
•
All versions are guaranteed to function for slower speeds.
PLCC
DS011329-3
Top
www.fairchildsemi.com
2
Absolute Maximum Ratings
(Note 1)
Storage Temperature
All Input Voltages except A9 with
Respect to Ground
V
PP
and A9 with Respect
to Ground
V
CC
Supply Voltage with
Respect to Ground
ESD Protection
−65˚C to +150˚C
−0.6V to +7V
−0.7V to +14V
− 0.6V to +7V
>
2000V
All Output Voltages with
Respect to Ground
V
CC
+ 1.0V to GND −0.6V
Operating Range
Range
Comm’l
Industrial
Temperature
0˚C to +70˚C
−40˚C to +85˚C
V
CC
+5V
±
10%
+5V
±
10%
Read Operation
DC Electrical Characteristics
Over Operating Range with V
PP
= V
CC
Symbol
V
IL
V
IH
V
OL
V
OH
I
SB1
I
SB2
I
CC1
I
PP
V
PP
I
LI
I
LO
Parameter
Input Low Level
Input High Level
Output Low Voltage
Output High Voltage
V
CC
Standby Current
(CMOS)
V
CC
Standby Current (T L)
V
CC
Active Current, T
2
L Inputs
V
PP
Supply Current
V
PP
Read Voltage
Input Load Current
Output Leakage Current
V
IN
= 5.5V or GND
V
OUT
= 5.5V or GND
2
Test Conditions
Min
−0.5
2.0
Max
0.8
V
CC
+ 1
0.4
Units
V
V
V
V
µA
mA
mA
µA
V
µA
µA
I
OL
= 2.1 mA
I
OH
= −2.5 mA
CE = V
CC
±
0.3V
V
IL
= GND
±
0.3V, V
IH
= V
CE = V
IH
CE = OE = V
IL
, f = 5 MHz
I/O = 0 mA
V
PP
= V
CC
3.5
100
CC
±
0.3V
1
35
10
GND
−1
−10
V
CC
1
10
AC Electrical Characteristics
Over Operating Range with V
PP
= V
CC
Symbol
t
ACC
t
CE
t
OE
t
CF
(Note 2)
t
DF
(Note 2)
t
OH
(Note 2)
Parameter
Min
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE High to Output Float
OE High to Output Float
Output Hold from Addresses, CE
or OE, Whichever Occurred First
0
90
Max
90
90
50
30
35
0
Min
120
Max
120
120
50
30
35
0
Min
150
Max
150
150
50
45
45
0
Min
200
Max
200
200
50
55
55
ns
ns
ns
ns
ns
Units
3
www.fairchildsemi.com
Capacitance
T
A
= +25˚C, f = 1 MHz (Note 2)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ
6
9
Max
12
12
Units
pF
pF
AC Test Conditions
Output Load
Input Rise and Fall Times
Input Pulse Levels
Timing Measurement Reference Level
Inputs
Outputs
1 TTL Gate and
C
L
= 100 pF (Note 8)
≤
5 ns
0.45 to 2.4V
(Note 10)
0.8V and 2.0V
0.8V and 2.0V
AC Waveforms
(Notes 6, 7, 9)
DS011329-4
Note 1:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is stress rating only and functional op-
eration of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect device reliability.
Note 2:
This parameter is only sampled and is not 100% tested.
Note 3:
OE may be delayed up to t
ACC
− t
OE
after the falling edge of CE without impacting t
ACC
.
Note 4:
The t
DF
and t
CF
compare level is determined as follows:
High to TRI-STATE
®
, the measured V
OH1
(DC) − 0.10V;
Low to TRI-STATE, the measured V
OL1
(DC) + 0.10V.
Note 5:
TRI-STATE may be attained using OE or CE .
Note 6:
The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 µF ceramic capacitor be used on
every device between V
CC
and GND.
Note 7:
The outputs must be restricted to V
CC
+ 1.0V to avoid latch-up and device damage.
Note 8:
TTL Gate: I
OL
= 1.6 mA, I
OH
= −400 µA.
C
L
= 100 pF includes fixture capacitance.
Note 9:
V
PP
may be connected to V
CC
except during programming.
Note 10:
Inputs and outputs can undershoot to −2.0V for 20 ns Max.
www.fairchildsemi.com
4
Programming Characteristics
(Notes 11, 12, 13, 14)
Symbol
t
AS
t
OES
t
CES
t
VPS
t
VCS
t
DS
t
AH
t
DH
t
DF
t
PW
t
OE
I
PP
I
CC
T
A
V
CC
V
PP
t
FR
V
IL
V
IH
t
IN
t
OUT
Parameter
Address Setup Time
OE Setup Time
CE Setup Time
V
PP
Setup Time
V
CC
Setup Time
Data Setup Time
Address Hold Time
Data Hold Time
Output Enable to Output Float Delay
Program Pulse Width
Data Valid from OE
V
PP
Supply Current
during Programming Pulse
V
CC
Supply Current
Temperature Ambient
Power Supply Voltage
Programming Supply Voltage
Input Rise, Fall Time
Input Low Voltage
Input High Voltage
Input Timing Reference Voltage
Output Timing Reference Voltage
2.4
0.8
0.8
20
6.25
12.5
5
0.0
4.0
2.0
2.0
0.45
25
6.5
12.75
50
30
6.75
13.0
mA
˚C
V
V
ns
V
V
V
V
CE = V
IL
CE = V
IL
CE = V
IL
OE = V
IH
Conditions
Min
1
1
1
1
1
1
0
1
0
45
50
60
105
100
30
Typ
Max
Units
µs
µs
µs
µs
µs
µs
µs
µs
ns
µs
ns
mA
Programming Waveforms
(Note 13)
DS011329-5
Note 11:
Fairchild’s standard product warranty applies to devices programmed to specifications described herein.
Note 12:
V
CC
must be applied simultaneously or before V
PP
and removed simultaneously or after V
PP
. The EPROM must not be inserted into or removed from a
board with voltage applied to V
PP
or V
CC
.
Note 13:
The maximum absolute allowable voltage which may be applied to the V
PP
pin during programming is 14V. Care must be taken when switching the V
PP
supply to prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1 µF capacitor is required across V
PP
, V
CC
to GND to suppress spu-
rious voltage transients which may damage the device.
Note 14:
During power up the PGM pin must be brought high (≥ V
IH
) either coincident with or before power is applied to V
