NM27C512 524 288-Bit (64K x 8) High Performance CMOS EPROM
February 1994
NM27C512
524 288-Bit (64K x 8) High Performance CMOS EPROM
General Description
The NM27C512 is a high performance 512K UV Erasable
Electrically Programmable Read Only Memory (EPROM) It
is manufactured using National’s proprietary 0 8 micron
CMOS AMG
TM
EPROM technology for an excellent combi-
nation of speed and economy while providing excellent reli-
ability
The NM27C512 provides microprocessor-based systems
storage capacity for portions of operating system and appli-
cation software Its 90 ns access time provides no-
wait-state operation with high-performance CPUs The
NM27C512 offers a single chip solution for the code storage
requirements of 100% firmware-based equipment Fre-
quently-used software routines are quickly executed from
EPROM storage greatly enhancing system utility
The NM27C512 is configured in the standard JEDEC
EPROM pinout which provides an easy upgrade path for
systems which are currently using standard EPROMs
The NM27C512 is one member of a high density EPROM
Family which range in densities up to 4 Megabit
Features
Y
Y
Y
Y
High performance CMOS
90 ns access time
Fast turn-off for microprocessor compatibility
Manufacturers identification code
JEDEC standard pin configuration
28-pin DIP package
32-pin chip carrier
Block Diagram
TL D 10834 – 1
TRI-STATE is a registered trademark of National Semiconductor Corporation
NSC800
TM
is a trademark of National Semiconductor Corporation
AMG
TM
is a trademark of WSI Inc
C
1995 National Semiconductor Corporation
TL D 10834
RRD-B30M65 Printed in U S A
Connection Diagrams
27C080 27C040 27C020 27C010 27C256
A
19
XX V
PP
XX V
PP
XX V
PP
A
16
A
16
A
16
A
16
A
15
A
15
A
15
A
15
V
PP
A
12
A
12
A
12
A
12
A
12
A
7
A
7
A
7
A
7
A
7
A
6
A
6
A
6
A
6
A
6
A
5
A
5
A
5
A
5
A
5
A
4
A
4
A
4
A
4
A
4
A
3
A
3
A
3
A
3
A
3
A
2
A
2
A
2
A
2
A
2
A
1
A
1
A
1
A
1
A
1
A
0
A
0
A
0
A
0
A
0
O
0
O
0
O
0
O
0
O
0
O
1
O
1
O
1
O
1
O
1
O
2
O
2
O
2
O
2
O
2
GND
GND
GND
GND
GND
DIP
NM27C512
27C256
27C010
27C020
27C040
27C080
V
CC
V
CC
V
CC
V
CC
XX PGM XX PGM
A
18
A
18
V
CC
XX
A
17
A
17
A
17
A
14
A
14
A
14
A
14
A
14
A
13
A
13
A
13
A
13
A
13
A
8
A
8
A
8
A
8
A
8
A
9
A
9
A
9
A
9
A
9
A
11
A
11
A
11
A
11
A
11
OE
OE
OE
OE
OE
VPP
A
10
A
10
A
10
A
10
A
10
CE PGM
CE
CE
CE PGM CE PGM
O
7
O
7
O
7
O
7
O
7
O
6
O
6
O
6
O
6
O
6
O
5
O
5
O
5
O
5
O
5
O
4
O
4
O
4
O
4
O
4
O
3
O
3
O
3
O
3
O
3
TL D 10834 – 2
Note
Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27C512 pins
Commercial Temp Range (0 C to
a
70 C)
Parameter Order Number
NM27C512 Q N V 90
NM27C512 Q N V 120
NM27C512 Q N V 150
NM27C512 Q N V 200
Access Time (ns)
90
120
150
200
Extended Temp Range (
b
40 C to
a
85 C)
Parameter Order Number
NM27C512 QE NE VE 90
NM27C512 QE NE VE 120
NM27C512 QE NE VE 150
NM27C512 QE NE VE 200
Access Time (ns)
90
120
150
200
Military Temp Range (
b
55 C to
a
125 C)
Parameter Order Number
NM27C512 QM 200
Access Time (ns)
200
Note
Surface mount PLCC package available for commercial and extended
temperature ranges only
All versions are guaranteed to function for slower speeds
Package Types NM27C512 Q N V XXX
Q
e
Quartz-Windowed Ceramic DIP Package
N
e
Plastic OTP DIP Package
V
e
PLCC Package
All packages conform to the JEDEC standard
Pin Names
A0 –A15
CE
OE
O0–O7
PGM
XX
Addresses
Chip Enable
Output Enable
Outputs
Program
Don’t Care (During Read)
PLCC
TL D 10834 – 3
2
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Storage Temperature
All Input Voltages Except A9 with
Respect to Ground
V
PP
and A9 with Respect to Ground
b
65 C to
a
150 C
b
0 6V to
a
7V
b
0 7V to
a
14V
V
CC
Supply Voltage with
Respect to Ground
ESD Protection
(MIL Std 883 Method 3015 2)
All Output Voltages with
Respect to Ground
b
0 6V to
a
7V
l
2000V
V
CC
a
1 0V to GND
b
0 6V
Operating Range
Range
Comm’l
Industrial
Military
Temperature
0 C to
a
70 C
b
40 C to
a
85 C
b
55 C to
a
125 C
V
CC
a
5V
a
5V
a
5V
Tolerance
g
10%
g
10%
g
10%
Read Operation
DC Electrical Characteristics
Symbol
V
IL
V
IH
V
OL
V
OH
I
SB1
I
SB2
I
CC1
I
CC2
Parameter
Input Low Level
Input High Level
Output Low Voltage
Output High Voltage
V
CC
Standby Current (CMOS)
V
CC
Standby Current
V
CC
Active Current
V
CC
Active Current
CMOS Inputs
V
PP
Supply Current
V
PP
Read Voltage
Input Load Current
Output Leakage Current
V
IN
e
5 5V or GND
V
OUT
e
5 5V or GND
I
OL
e
2 1 mA
I
OH
e b
2 5 mA
CE
e
V
CC
g
0 3V
CE
e
V
IH
CE
e
OE
e
V
IL
f
e
5 MHz
CE
e
GND f
e
5 MHz
Inputs
e
V
CC
or GND I O
e
0 mA
C I Temp Ranges
V
PP
e
V
CC
V
C
b
0 7
b
1
b
10
Test Conditions
Min
b
0 5
Max
08
V
CC
a
1
04
Units
V
V
V
V
mA
mA
mA
mA
mA
V
mA
mA
20
35
100
1
40
35
10
V
CC
1
10
I
PP
V
PP
I
LI
I
LO
AC Electrical Characteristics
Symbol
t
ACC
t
CE
t
OE
t
DF
t
OH
Parameter
Min
Address to Output
Delay
CE to Output Delay
OE to Output Delay
Output Disable to
Output Float
Output Hold from
Addresses CE or OE
Whichever Occurred First
0
90
Max
90
90
40
35
Min
120
Max
120
120
50
25
Min
150
Max
150
150
50
45
Min
200
Max
200
200
50
ns
55
Units
0
0
3
Capacitance
T
A
e a
25 C
Symbol
C
IN1
C
OUT
C
IN2
f
e
1 MHz (Note 2)
Parameter
Input Capacitance
except OE V
PP
Output Capacitance
OE V
PP
Input
Capacitance
Conditions
V
IN
e
0V
V
OUT
e
0V
V
IN
e
0V
Typ
6
9
20
Max
12
12
25
Units
pF
pF
pF
AC Test Conditions
Output Load
Input Rise and Fall Times
Input Pulse Levels
1 TTL Gate and
C
L
e
100 pF (Note 8)
s
5 ns
0 45V to 2 4V
Timing Measurement Reference Level (Note 9)
Inputs
0 8V and 2V
Outputs
0 8V and 2V
AC Waveforms
(Notes 6
7)
TL D 10834 – 4
Note 1
Stresses above those listed under ‘‘Absolute Maximum Ratings’’ may cause permanent damage to the device This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute
maximum rating conditions for extended periods may affect device reliability
Note 2
This parameter is only sampled and is not 100% tested
Note 3
OE may be delayed up to t
ACC
– t
OE
after the falling edge of CE without impacting t
ACC
Note 4
The t
DF
and t
CF
compare level is determined as follows
High to TRI-STATE the measured V
OH1
(DC)
b
0 10V
Low to TRI-STATE the measured V
OL1
(DC)
a
0 10V
Note 5
TRI-STATE may be attained using OE or CE
Note 6
The power switching characteristics of EPROMs require careful device decoupling It is recommended that at least a 0 1
mF
ceramic capacitor be used on
every device between V
CC
and GND
Note 7
The outputs must be restricted to V
CC
a
1 0V to avoid latch-up and device damage
Note 8
1 TTL Gate I
OL
e
1 6 mA I
OH
e b
400
mA
C
L
100 pF includes fixture capacitance
Note 9
Inputs and outputs can undershoot to
b
2 0V for 20 ns Max
4
Programming Characteristics
(Notes 1 and 2)
Symbol
t
AS
t
OES
t
DS
t
VCS
t
AH
t
DH
t
CF
t
PW
t
OEH
t
DV
t
PRT
t
VR
I
PP
I
CC
T
R
V
CC
V
PP
t
FR
V
IL
V
IH
t
IN
t
OUT
Parameter
Address Setup Time
OE Setup Time
Data Setup Time
V
CC
Setup Time
Address Hold Time
Data Hold Time
Chip Enable to Output Float Delay
Program Pulse Width
OE Hold Time
Data Valid from CE
OE Pulse Rise Time
during Programming
V
PP
Recovery Time
V
PP
Supply Current during
Programming Pulse
V
CC
Supply Current
Temperature Ambient
Power Supply Voltage
Programming Supply Voltage
Input Rise Fall Time
Input Low Voltage
Input High Voltage
Input Timing Reference Voltage
Output Timing Reference Voltage
24
08
08
20
6
12 5
5
0
4
2
2
0 45
25
6 25
12 75
CE
e
V
IL
OE
e
V
PP
OE
e
V
IL
50
1
30
50
30
65
13
OE
e
V
IL
Conditions
Min
1
1
1
1
0
1
0
95
1
250
100
60
105
Typ
Max
Units
ms
ms
ms
ms
ms
ms
ns
ms
ms
ns
ns
ms
mA
mA
C
V
V
ns
V
V
V
V
Programming Waveforms
TL D 10834 – 5
Note 1
National’s standard product warranty applies to devices programmed to specifications described herein
Note 2
V
CC
must be applied simultaneously or before V
PP
and removed simultaneously or after V
PP
The EPROM must not be inserted into or removed from a
board with voltage applied to V
PP
or V
CC
Note 3
The maximum absolute allowable voltage which may be applied to the V
PP
pin during programming is 14V Care must be taken when switching the V
PP
supply to prevent any overshoot from exceeding this 14V maximum specification At least a 0 1
mF
capacitor is required across V
CC
to GND to suppress spurious
voltage transients which may damage the device
Note 4
Programming and program verify are tested with the fast Program Algorithm at typical power supply voltages and timings
stm32/stm8
