NPIC6C595
Power logic 8-bit shift register; open-drain outputs
Rev. 1 — 20 August 2012
Product data sheet
1. General description
The NPIC6C595 is an 8-bit serial-in/serial or parallel-out shift register with a storage
register and open-drain outputs. Both the shift and storage register have separate clocks.
The device features a serial input (DS) and a serial output (Q7S) to enable cascading and
an asynchronous reset input (MR). A LOW on MR resets both the shift register and
storage register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The
data in the shift register is transferred to the storage register on a LOW-to-HIGH transition
of the STCP input and to the Q7S output on a LOW-to-HIGH transition of the SHCP input.
If both clocks are connected together, the shift register is always one clock pulse ahead of
the storage register. Data in the storage register drives the gate of the output
extended-drain NMOS transistor whenever the output enable input (OE) is LOW. A HIGH
on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE
input does not affect the state of the registers. The open-drain outputs are 33 V/100 mA
continuous current extended-drain NMOS transistors designed for use in systems that
require moderate load power such as LEDs. Integrated voltage clamps in the outputs
provide protection against inductive transients. This feature makes the device suitable for
power driver applications such as relay, solenoids and other low-current or
medium-voltage loads.
2. Features and benefits
Specified from
40 C
to +125
C
Low R
DSon
Eight Power EDNMOS transistor outputs of 100 mA continuous current
250 mA current limit capability
Output clamping voltage 33 V
30 mJ avalanche energy capability
All registers cleared with single input
Low power consumption
ESD protection:
HBM JDS-001 Class 2 exceeds 2500 V
CDM JESD22-C101E exceeds 1000 V
3. Applications
LED sign
Graphic status panel
Fault status indicator
NXP Semiconductors
NPIC6C595
Power logic 8-bit shift register; open-drain outputs
4. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
NPIC6C595D
NPIC6C595PW
NPIC6C595BQ
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
SO16
TSSOP16
Description
plastic small outline package; 16 leads;
body width 3.9 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
Version
SOT109-1
SOT403-1
Type number
DHVQFN16 plastic dual in-line compatible thermal enhanced
SOT763-1
very thin quad flat package; no leads; 16 terminals;
body 2.5
3.5
0.85 mm
5. Functional diagram
15
SHCP
10
STCP
Q0
Q1
Q2
2
3
4
5
6
11
12
13
14
9
8
10
15
7
DS
SHCP
MR
Q7S
STCP
9
8-STAGE SHIFT REGISTER
2
DS
Q3
Q4
Q5
Q6
Q7
Q7S
8-BIT STORAGE REGISTER
OE
OPEN-DRAIN OUTPUTS
Q0 Q1 Q2
3
4
5
Q3 Q4 Q5 Q6 Q7
6
11
12
13
14
aaa-002542
MR
7
OE
8
aaa-002547
Fig 1.
Logic symbol
Fig 2.
Functional diagram
V
CC
Qn
33 V
GND
aaa-002550
GND
aaa-002551
Fig 3.
Schematic of all inputs
Fig 4.
Schematic of open-drain outputs (Qn)
NPIC6C595
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 20 August 2012
2 of 20
NXP Semiconductors
NPIC6C595
Power logic 8-bit shift register; open-drain outputs
STAGE 0
DS
D
Q
LATCH
0
CP
R
D
STAGE 1 TO 6
Q
STAGE 7
D
Q
LATCH
7
CP
R
Q7S
SHCP
MR
D
R
Q
D
R
Q
LATCH
CP
LATCH
CP
STCP
OE
GND
GND
aaa-002543
Q0
Q1 Q2 Q3 Q4 Q5 Q6
Q7
Fig 5.
Logic diagram
7
SHCP
6
5
4
3
2
1
0
5V
GND
5V
GND
5V
GND
5V
GND
5V
GND
V
OH
V
OL
aaa-002553
OE
DS
STCP
MR
Q1
Fig 6.
Timing diagram
NPIC6C595
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 20 August 2012
3 of 20
NXP Semiconductors
NPIC6C595
Power logic 8-bit shift register; open-drain outputs
6. Pinning information
6.1 Pinning
NPIC6C595
terminal 1
index area
16 GND
15 SHCP
14 Q7
13 Q6
12 Q5
GND
(1)
8
9
Q7S
11 Q4
10 STCP
OE
V
CC
2
3
4
5
6
7
1
DS
V
CC
DS
Q0
Q1
Q2
Q3
MR
OE
1
2
3
4
5
6
7
8
aaa-003482
NPIC6C595
16 GND
15 SHCP
14 Q7
13 Q6
12 Q5
11 Q4
10 STCP
9
Q7S
Q0
Q1
Q2
Q3
MR
aaa-003483
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 7.
Pin configuration SO16 and TSSOP16
Fig 8.
Pin configuration DHVQFN16
6.2 Pin description
Table 2.
Symbol
V
CC
DS
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
MR
OE
Q7S
STCP
SHCP
GND
Pin description
Pin
1
2
3, 4, 5, 6, 11, 12, 13, 14
7
8
9
10
15
16
Description
supply voltage
serial data input
parallel data output (open-drain)
master reset (active LOW)
output enable input (active LOW)
serial data output
storage register clock input
shift register clock input
ground (0 V)
NPIC6C595
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 20 August 2012
4 of 20
NXP Semiconductors
NPIC6C595
Power logic 8-bit shift register; open-drain outputs
7. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
DS
I
d(SD)
I
D
Parameter
supply voltage
input voltage
drain-source voltage
source-drain diode current
drain current
power EDNMOS drain-source
voltage
continuous
pulsed
T
amb
= 25
C
continuous; each output;
all outputs on
pulsed; each output;
all outputs on
I
DM
E
AS
I
AL
T
stg
P
tot
peak drain current
avalanche current
storage temperature
total power dissipation
T
amb
= 25
C
SO16
TSSOP16
DHVQFN16
T
amb
= 125
C
SO16
TSSOP16
DHVQFN16
[1]
[2]
[3]
[4]
Each power EDNMOS source is internally connected to GND.
Pulse duration
100
s
and duty cycle
2 %.
V
DS
= 15 V; starting junction temperature (T
j
) = 25
C;
L = 1.5 H; avalanche current (I
AL
) = 200 mA.
For SO16 packages: above 25
C
the value of P
tot
derates linearly with 6.4 mW/
C
.
For TSSOP16 packages: above 25
C
the value of P
tot
derates linearly with 5.8 mW/
C
.
For DHVQFN16 packages: above 25
C
the value of P
tot
derates linearly with 14.6 mW/
C
.
[4]
[4]
[2]
[2]
[1]
Conditions
Min
0.5
0.3
-
-
-
-
-
-
-
-
65
-
-
-
-
-
-
Max
+7.0
+7.0
+33
250
500
100
250
250
30
200
+150
800
725
1825
160
145
365
Unit
V
V
V
mA
mA
mA
mA
mA
mJ
mA
C
mW
mW
mW
mW
mW
mW
single output; T
amb
= 25
C
see
Figure 9
[2]
[3]
[3]
non-repetitive avalanche energy single pulse; see
Figure 9
NPIC6C595
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 20 August 2012
5 of 20
