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NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G

NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G

NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)

512MB, 256MB and 128MB

PC3200, PC2700 and PC2100

Unbuffered DDR DIMM

184 pin Unbuffered DDR DIMM

Based on DDR400/333/266 256M bit B Die device

Features

• 184 Dual In-Line Memory Module (DIMM)

• Unbuffered DDR DIMM based on 256M bit die B device,

organized as either 32Mbx8 or 16Mbx16

• Performance:

PC3200 PC2700 PC2100

Speed Sort

DIMM

CAS

Latency

Clock Frequency

Clock Cycle

200

400

2.5

166

333

75B

2.5

133

7.5

266

MHz

Unit

• DRAM DLL aligns DQ and DQS transitions with clock transitions

• Address and control signals are fully synchronous to positive

clock edge

• Programmable Operation:

- DIMM

CAS

Latency: 2, 2.5, 3

- Burst Type: Sequential or Interleave

- Burst Length: 2, 4, 8

- Operation: Burst Read and Write

• Auto Refresh (CBR) and Self Refresh Modes

• Automatic and controlled precharge commands

• 7.8

µs

Max. Average Periodic Refresh Interval

• Serial Presence Detect EEPROM

• Gold contacts

• SDRAMs are packaged in TSOP packages

• “Green” packaging – lead free

DQ Burst Frequency

• Intended for 133, 166 and 200 MHz applications

• Inputs and outputs are SSTL-2 compatible

• V

= V

DDQ

= 2.5V ± 0.2V (2.6V ± 0.1V for PC3200)

• SDRAMs have 4 internal banks for concurrent operation

• Differential clock inputs

• Data is read or written on both clock edges

Description

NT512D64S8HB0G, NT512D64S8HB1G, NT512D64S8HB1GY, NT512D72S8PB0G, NT256D64SH88B0G, NT256D64SH88B1G,

NT256D64SH88B1GY, NT256D72S89B0G and NT128D64SH4B1G are unbuffered 184-Pin Double Data Rate (DDR) Synchronous DRAM

Dual In-Line Memory Modules (DIMM). NT512D64S8HB1GY and NT256D64SH88B1GY are packaged using lead free technology.

NT512D64S8HB0G, NT512D64S8HB1G and NT512D64S8HB1GY are 512MB modules organized as dual ranks using sixteen 32Mx8

TSOP devices. NT512D72S8PB0G has ECC and is organized as dual ranks using eighteen 32Mx8 TSOP devices. NT256D64SH88B0G,

NT256D64SH88B1G and NT256D64SH88B1GY are 256MB modules organized as single rank using eight 32Mx8 TSOP devices.

NT256D72S89B0G has ECC and is organized as single rank using nine 32Mx8 TSOP devices. NT128D64SH4B1G are 128MB modules,

organized as single rank using four 16Mx16 TSOP devices.

Depending on the speed grade, these DIMMs are intended for use in applications operating up to 200 MHz clock speeds and achieves

high-speed data transfer rates of up to 400 MHz. Prior to any access operation, the device

CAS

latency and burst type/ length/operation

type must be programmed into the DIMM by address inputs and I/O inputs BA0 and BA1 using the mode register set cycle.

The DIMM uses a serial EEPROM and through the use of a standard IIC protocol the serial presence-detect implementation (SPD) can be

accessed. The first 128 bytes of the SPD data are programmed with the module characteristics as defined by JEDEC.

REV 2.2

Aug 3, 2004

NANYA reserves the right to change products and specifications without notice.

Preliminary

NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G

NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G

NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)

Unbuffered DDR DIMM

Ordering Information

Part Number

NT512D72S8PB0G-5T

Organization

Speed

Power

Leads

64Mx72

NT512D64S8HB1G-5T

64Mx64

NT512D64S8HB1GY-5T

(lead free)

NT256D72S890G-5T

PC3200 200MHz (5ns @ CL = 3)

32Mx72

DDR400

3-3-3

166MHz (6ns @ CL = 2.5)

2.6V

NT256D64S88B1G-5T

32Mx64

NT256D64S88B1GY-5T

(lead free)

NT128D64SH4B1G-5T

16Mx64

NT512D64S8HB1G-6K

64Mx64

NT512D64S8HB1GY-6K

(lead free)

NT256D64S88B1GY-6K

(lead free)

32Mx64

NT256D64S88B0G-6K

2.5V

NT128D64SH4B1G-6K

16Mx64

PC2700 166MHz (6ns @ CL = 2.5)

DDR333

2.5-3-3 133MHz (7.5ns @ CL = 2)

Gold

NT512D64S8HB0G-75B

64Mx64

PC2100 133MHz (7.5ns @ CL = 2.5)

32Mx64

DDR266B

2.5-3-3 100MHz (10ns @ CL = 2)

NT256D64S88B0G-75B

NT128D64SH4B1G-75B

16Mx64

For the closest sales office or information, please visit:

www.nanya.com

Nanya Technology Corporation

Hwa Ya Technology Park 669

Fu Hsing 3rd Rd., Kueishan,

Taoyuan, 333, Taiwan, R.O.C.

Tel: +886-3-328-1688

REV 2.2

Aug 3, 2004

NANYA reserves the right to change products and specifications without notice.

Preliminary

NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G

NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G

NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)

Unbuffered DDR DIMM

Pin Description

CK0, CK1, CK2,

CK0, CK1, CK2

CKE0, CKE1

RAS

CAS

S0, S1

A0-A9, A11, A12

A10/AP

BA0, BA1

REF

DDID

Differential Clock Inputs.

Clock Enable

Row Address Strobe

Column Address Strobe

Write Enable

Chip Selects

Address Inputs

Address Input/Auto-precharge

SDRAM Bank Address Inputs

Ref. Voltage for SSTL_2 inputs

Identification flag.

DQ0-DQ63

DQS0-DQS7

DM0-DM7

DDQ

SCL

SDA

SA0-2

DDSPD

Data input/output

Bidirectional data strobes

Input Data Mask

Power

Supply voltage for DQs

Ground

No Connect

Serial Presence Detect Clock Input

Serial Presence Detect Data input/output

Serial Presence Detect Address Inputs

Serial EEPROM positive power supply

Pinout

Front

REF

DQ0

DQ1

DQS0

DQ2

DQ3

DQ8

DQ9

DQS1

DDQ

CK1

DQ10

DQ11

CKE0

DDQ

DQ16

DQ17

DQS2

DQ18

DDQ

DQ19

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

Back

DQ4

DQ5

DDQ

DM0/DQS9

DQ6

DQ7

DDQ

DQ12

DQ13

DM1/DQS10

DQ14

DQ15

CKE1

DDQ

DQ20

A12

DQ21

A11

DM2/DQS11

DQ22

DQ23

KEY

DQ32

DDQ

DQ33

DQS4

DQ34

BA0

DQ35

DQ40

Front

DQ24

DQ25

DQS3

DQ26

DQ27

BA1

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

KEY

145

146

147

148

149

150

151

152

153

DQ36

DQ37

DM4/DQS13

DQ38

DQ39

DQ44

Back

DQ28

DQ29

DDQ

DM3/DQS12

DQ30

DQ31

DDQ

CK0

A10

DDQ

Front

DDQ

DQ41

CAS

DQS5

DQ42

DQ43

DQ48

DQ49

CK2

DDQ

DQS6

DQ50

DQ51

DDID

DQ56

DQ57

DQS7

DQ58

DQ59

SDA

SCL

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

Back

RAS

DQ45

DDQ

DM5/DQS14

DQ46

DQ47

DDQ

DQ52

DQ53

DM6/DQS15

DQ54

DQ55

DDQ

DQ60

DQ61

DM7/DQS16

DQ62

DQ63

DDQ

SA0

SA1

SA2

DDSPD

Note: All pin assignments are consistent for all 8-byte unbuffered versions.

REV 2.2

Aug 3, 2004

NANYA reserves the right to change products and specifications without notice.

Preliminary

NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G

NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G

NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)

Unbuffered DDR DIMM

Input/Output Functional Description

Symbol

CK0, CK1, CK2,

CK0, CK1, CK2

(SSTL)

Type

Polarity

Cross

point

Active

High

Function

The system clock inputs. All address and command lines are sampled on the cross point of

the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is driven

from the clock inputs and output timing for read operations is synchronized to the input

clock.

Activates the DDR SDRAM CK signal when high and deactivates the CK signal when low.

By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh

mode.

Enables the associated DDR SDRAM command decoder when low and disables the

S0, S1

(SSTL)

Active

Low

Active

Low

command decoder when high. When the command decoder is disabled, new commands are

ignored but previous operations continue. Physical Bank 0 is selected by S0; Bank 1 is

selected by S1.

RAS, CAS, WE

REF

DDQ

BA0, BA1

(SSTL)

Supply

(SSTL)

When sampled at the positive rising edge of the clock,

RAS, CAS, WE

define the operation to

be executed by the SDRAM.

Reference voltage for SSTL-2 inputs

Isolated power supply for the DDR SDRAM output buffers to provide improved noise

immunity

Selects which SDRAM bank is to be active.

During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when

sampled at the rising clock edge.

During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)

when sampled at the rising clock edge. In addition to the column address, AP is used to

A0 - A9

A10/AP

A11, A12

(SSTL)

invoke auto-precharge operation at the end of the Burst Read or Write cycle. If AP is high,

auto-precharge is selected and BA0/BA1 defines the bank to be precharged. If AP is low,

auto-precharge is disabled.

During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control

which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the

state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge.

DQ0 - DQ63

DQS0 - DQS7,

DQS9 – DQS16

CB0 – CB7

DM0 – DM8

, V

SA0 – SA2

SDA

SCL

DDSPD

Supply

(SSTL)

Input

Supply

Active

High

Active

High

Data and Check Bit input/output pins operate in the same manner as on conventional

DRAMs.

Data strobes: Output with read data, input with write data. Edge aligned with read data,

centered on write data. Used to capture write data.

Data Check Bit Input/Output pins. Used on ECC modules and is not used on x64 modules.

The data write masks, associated with one data byte. In Write mode, DM operates as a byte

mask by allowing input data to be written if it is low but blocks the write operation if it is high.

In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is

not used on x64 modules.

Power and ground for the DDR SDRAM input buffers and core logic

Address inputs. Connected to either V

or V

on the system board to configure the Serial

Presence Detect EEPROM address.

This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor

must be connected from the SDA bus line to V DD to act as a pull-up.

This signal is used to clock data into and out of the SPD EEPROM. A resistor may be

connected from the SCL bus time to V DD to act as a pull-up.

Serial EEPROM positive power supply.

CKE0, CKE1

(SSTL)

REV 2.2

Aug 3, 2004

NANYA reserves the right to change products and specifications without notice.

Preliminary

NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G

NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G

NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)

Unbuffered DDR DIMM

Functional Block Diagram

2 Ranks, 16 devices, 32Mx8 DDR SDRAMs

DQS0

DM0/DQS9

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQS1

DM1/DQS10

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS2

DM2/DQS11

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQS3

DM3/DQS12

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQS

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DQS

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQS

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DQS

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQS7

DM7/DQS16

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQS

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DQS

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQS

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DQS

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQS6

DM6/DQS15

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQS

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DQS

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQS

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DQS

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQS5

DM5/DQS14

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQS

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DQS

DQS4

DM4/DQS13

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DQS

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DQS

D12

D13

D10

D14

D11

D15

BA0-BA1

A0-A13

RAS

CAS

CKE0

CKE1

Notes :

BA0-BA1 : SDRAMs D0-D15

A0-A13 : SDRAMs D0-D15

RAS

: SDRAMs D0-D15

CAS

: SDRAMs D0-D15

CKE : SDRAMs D0-D7

CKE : SDRAMs D8-D15

: SDRAMs D0-D15

DDSPD

DDQ

REF

DDID

SPD

D0-D15

Strap: see Note 4

Serial PD

* Clock Wiring

Clock Input

SDRAMs

*CK0/CK0

4 SDRAMs

*CK1/CK1

6 SDRAMs

*CK2/CK2

6 SDRAMs

* Wire per Clock Loading Table/

Wiring Diagrams

SCL

SA0

SA1

SA2

SDA

DQ-to-I/O wiring is shown as recommended but may be changed.

DQ/DQS/DM/CKE/S relationships must be maintained as shown.

DQ, DQS, DM/DQS resistors: 22 Ohms.

DDID

strap connections (for memory device V

, V

DDQ

STRAP OUT (OPEN): V

= V

DDQ

STRAP IN (V

): V

is not equal to V

DDQ

REV 2.2

Aug 3, 2004

NANYA reserves the right to change products and specifications without notice.

Preliminary