NX3DV642
3-lane high-speed MIPI compatible switch
Rev. 1 — 20 August 2012
Product data sheet
1. General description
The NX3DV642 is a high-speed triple-pole double-throw differential signal switch. The
device is optimized for switching between two MIPI devices, such as cameras or LCD
displays and on-board multimedia application processors.
The NX3DV642 is compatible with the requirements of Mobile Industry Processor
Interface (MIPI). The low capacitance design allows the NX3DV642 to switch signals that
exceed 500 MHz in frequency
2. Features and benefits
Supply voltage range from 2.65 V to 4.3 V
7.5
typical ON resistance
8.4 pF typical ON capacitance
950 MHz typical bandwidth or data frequency
Low crosstalk of
55
dB at 100 MHz
Break-before-make switching
ESD protection:
HBM JESD22-A114F Class 2 exceeds 2000 V
CDM AEC-Q100-011 revision B exceeds 1000 V
HBM exceeds 12000 V for power to GND protection
Latch-up performance exceeds 100 mA per JESD 78 Class II Level A
Specified from
40 C
to +85
C
3. Applications
Dual camera applications for cell phones
Dual LCD applications for cell phones, digital camera displays and viewfinders
4. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
NX3DV642GU
40 C
to +85
C
XQFN24
Description
plastic, extremely thin quad flat package; no leads;
24 terminals; body 2.5 x 3.4 x 0.5 mm
Version
SOT1310-1
Type number
NXP Semiconductors
NX3DV642
3-lane high-speed MIPI compatible switch
5. Marking
Table 2.
Marking
Marking code
3DV642
Type number
NX3DV642GU
6. Functional diagram
1
CLK+
CLK1+
CLK2+
CLK1-
CLK2-
1D1+
1D2+
1D1-
1D2-
2D1+
2D2+
2D1-
2D2-
17
22
16
23
15
20
14
21
13
19
12
18
2
CLK-
3
1D+
4
1D-
5
2D+
6
2D-
8
11
OE
S
CONTROL
LOGIC
aaa-002567
Fig 1.
Logic symbol
CAMERA 1
D D
C
CAMERA 2
C
D D
LCD 1
D D
C
LCD 2
D D
C
NX3DV642
NX3DV642
D D
C
MAP PROCESSOR
D D
C
MAP PROCESSOR
aaa-002568
Fig 2.
Application block diagram
NX3DV642
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 20 August 2012
2 of 16
NXP Semiconductors
NX3DV642
3-lane high-speed MIPI compatible switch
7. Pinning information
7.1 Pinning
NX3DV642
CLK2+
CLK2-
1D2+
20
2D2+
19
18
17
16
15
14
13
8
OE
9
GND
10
V
CC
11
S
12
2D1-
aaa-002569
terminal 1
index area
CLK+
CLK-
1D+
1D-
2D+
2D-
24
1
2
3
4
5
6
7
n.c.
23
22
21
1D2-
n.c.
2D2-
CLK1+
CLK1-
1D1+
1D1-
2D1+
Transparent top view
Fig 3.
Pin configuration SOT1310-1 (XQFN24)
7.2 Pin description
Table 3.
Symbol
CLK+, CLK
1D+, 1D
2D+, 2D
n.c.
OE
GND
V
CC
S
2D1+, 2D1
1D1+, 1D1
CLK1+, CLK1
2D2+, 2D2
1D2+, 1D2
CLK2+, CLK2
Pin description
Pin
1, 2
3, 4
5, 6
7, 24
8
9
10
11
13, 12
15, 14
17, 16
19, 18
20, 21
22, 23
Description
common output or input clock path
common output or input data path 1D
common output or input data path 2D
not connected
output enable input (active LOW)
ground (0 V)
supply voltage
select input
independent input or output data path 2D1
independent input or output data path 1D1
independent input or output clock path CLK1
independent input or output data path 2D2
independent input or output data path 1D2
independent input or output clock path CLK2
NX3DV642
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 20 August 2012
3 of 16
NXP Semiconductors
NX3DV642
3-lane high-speed MIPI compatible switch
8. Functional description
Table 4.
Input
S
L
H
X
[1]
Function table
[1]
Channel on
OE
L
L
H
CLKn, 1Dn, 2Dn = CLK1n, 1D1n, 2D1n
CLKn, 1Dn, 2Dn = CLK2n, 1D2n, 2D2n
switch off
H = HIGH voltage level; L = LOW voltage level; X = don’t care. (n = + or
)
9. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
SW
I
IK
I
SK
I
SW
I
CC
T
stg
P
tot
[1]
Parameter
supply voltage
input voltage
switch voltage
input clamping current
switch clamping current
switch current
supply current
storage temperature
total power dissipation
Conditions
pins S and OE
V
I
<
0.5
V
V
I
<
0.5
V
[1]
Min
0.5
0.5
0.5
50
50
100
-
65
Max
+5.5
+5.5
+5.5
-
+50
+100
+50
+150
533
Unit
V
V
V
mA
mA
mA
mA
C
mW
T
amb
=
40 C
to +85
C
-
The minimum input voltage rating may be exceeded if the input current rating is observed.
10. Recommended operating conditions
Table 6.
V
CC
V
I
V
SW
T
amb
[1]
Recommended operating conditions
Conditions
pins S and OE
[1]
Symbol Parameter
supply voltage
input voltage
switch voltage
ambient temperature
Min
2.65
0
0
40
Max
4.3
4.3
4.5
+85
Unit
V
V
V
C
To avoid sinking GND current from terminals CLKn, 1Dn and 2Dn when switch current flows in terminals CLK1n, CLK2n, 1D1n 1D2n,
2D1n and 2D2n (n = + or
),
the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into
terminals CLKn, 1Dn and 2Dn, no GND current flows from terminals CLK1n, CLK2n, 1D1n 1D2n, 2D1n and 2D2n. In this case, there is
no limit for the voltage drop across the switch.
NX3DV642
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 20 August 2012
4 of 16
NXP Semiconductors
NX3DV642
3-lane high-speed MIPI compatible switch
11. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground 0 V).
Symbol
V
IH
V
IL
V
IK
I
I
I
S(OFF)
I
OFF
I
CC
I
CC
Parameter
HIGH-level input
voltage
LOW-level input
voltage
input clamping
voltage
input leakage
current
OFF-state leakage
current
power-off leakage
current
supply current
additional supply
current
input capacitance
OFF-state
capacitance
ON-state
capacitance
Conditions
V
CC
= 2.65 V to 2.775 V
V
CC
= 4.3 V
V
CC
= 2.65 V to 2.775 V
V
CC
= 4.3 V
V
CC
= 2.775 V; I
I
=
18
mA
pins S and OE; V
I
= GND to 4.3 V;
V
CC
= 4.3 V
V
CC
= 4.3 V; see
Figure 4
V
I
or V
O
= 0 V to 4.3 V; V
CC
= 0 V
V
I
= V
CC
or GND; V
SW
= GND or
V
CC
; V
CC
= 4.3 V
V
I
= 1.8 V; V
SW
= GND or V
CC
;
V
CC
= 2.775 V
pins S and OE
pins CLK1n, CLK2n, 1D1n 1D2n,
2D1n and 2D2n; V
I
= 0 V to 3.3 V
pins CLKn, 1Dn and 2Dn;
V
I
= 0 V to 3.3 V
[2]
T
amb
=
40 C
to +85
C
Min
1.3
1.7
-
-
1.2
-
-
-
-
-
Typ
[1]
-
-
-
-
-
-
-
-
-
-
Max
-
-
0.5
0.7
-
1
2
2
2
1.5
Unit
V
V
V
V
V
A
A
A
A
A
C
I
C
S(OFF)
C
S(ON)
-
-
-
1.3
3.0
8.4
-
-
-
pF
pF
pF
[2]
[1]
[2]
Typical values are measured at T
amb
= 25
C
and V
CC
= 2.775 V.
n = + or
.
11.1 Test circuits
V
CC
switch
1
V
IL
or V
IH
S
1Dn
OE
V
IH
VI
S
V
IL
V
IH
1D1n
1D2n
GND
1
2
2
switch
I
S
VO
aaa-002570
V
I
= V
CC
or GND and V
O
= GND or V
CC
.
Test circuit also applies for 2Dn, 2D1n, 2D2n CLKn, CLK1n and CLK2n (n = + or
).
Fig 4.
NX3DV642
Test circuit for measuring OFF-state leakage current
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 20 August 2012
5 of 16
