NX5DV713
Dual supply 1-of-2 VGA switch
Rev. 1 — 24 November 2011
Product data sheet
1. General description
The NX5DV713 is a dual supply 1-to-2 VGA switch. It integrates high-bandwidth SPDT
switches with level-translating buffers and level translating switches to provide switching
of input RGB, H-sync, V-sync and DDC signals to either of two output channels.
The NX5DV713 is characterized for operation from
40 C
to +85
C.
2. Features and benefits
RGB switches:
Low ON resistance (4
typical)
Low ON capacitance (12 pF typical)
Low output skew (50 ps)
Low power consumption (< 2
A)
Level translation of sync and DDC signals
Over-voltage tolerant inputs
ESD protection:
HBM JESD22-A114F Class 3A exceeds 4 kV
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101D exceeds 1000 V
IEC61000-4-2 contact discharge exceeds 4 kV for I/Os
Specified from
40 C
to +85
C
3. Applications
Notebook Computers
Docking stations
Digital projectors
Computer monitors
Servers
Storage
NXP Semiconductors
NX5DV713
Dual supply 1-of-2 VGA switch
4. Ordering information
Table 1.
Ordering information
Package
Temperature range
NX5DV713HF
40 C
to +85
C
Name
Description
Version
SOT1180-1
HWQFN32 plastic thermal enhanced very very thin quad flat
package; no leads; 32 terminals; body 3
6
0.75
mm
Type number
5. Functional diagram
VCC(B)
R0
G0
B0
R1
R2
G1
G2
B1
B2
VCC(A)
SEL
CONTROL LOGIC
H1
H0
LEVEL
TRANSLATING
MUX
H2
V1
V2
V0
RPU
RPU
SDA1
LEVEL
TRANSLATING
SWITCH
SCL1
RPU
RPU
RPU
RPU
SDA0
SCL0
SDA2
SCL2
aaa-001597
Fig 1.
Logic symbol
NX5DV713
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 24 November 2011
2 of 20
NXP Semiconductors
NX5DV713
Dual supply 1-of-2 VGA switch
6. Pinning information
6.1 Pinning
32 V
CC(A)
29 TEST
31 GND
terminal 1
index area
R0
G0
GND
V
CC(A)
B0
H0
V0
n.c.
SDA0
1
2
3
4
5
6
7
8
9
28 GND
27 R1
26 R2
25 G1
24 G2
23 n.c.
(2)
22 B1
21 B2
20 H1
19 H2
18 V1
17 V2
V
CC(B)
16
aaa-001608
NX5DV713
SCL0 10
GND 11
SDA1 12
GND
(1)
SDA2 13
SCL1 14
SCL2 15
Transparent top view
(1) This is not a supply pin, the substrate is attached to this pad using conductive die attach material. There is no electrical or
mechanical requirement to solder this pad however if it is soldered the solder land should remain floating or be connected to
GND.
(2) Pin can be connected to V
CC(A)
.
Fig 2.
Pin configuration SOT1180-1 (HWQFN32)
6.2 Pin description
Table 2.
Symbol
R0, G0, B0
GND
V
CC(A)
H0
V0
n.c.
SDA0
SCL0
SDA1, SDA2
SCL1, SCL2
V
CC(B)
V1, V2
NX5DV713
Pin description
Pin
1, 2, 5
3, 11, 28, 31
4, 32
6
7
8, 23
[2]
9
10
12, 13
14, 15
16
18, 17
All information provided in this document is subject to legal disclaimers.
30 SEL
Description
RGB input or output
ground (0 V)
supply voltage A
horizontal sync input
vertical sync input
not connected
SDA0 input or output
SCL0 input or output
SDAn input or output
SCLn input or output
supply voltage B
vertical sync output
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 24 November 2011
3 of 20
NXP Semiconductors
NX5DV713
Dual supply 1-of-2 VGA switch
Table 2.
Symbol
H1, H2
Pin description
…continued
Pin
20, 19
27, 25, 22, 26, 24, 21
29
30
Description
horizontal sync output
RGB input or output
test pin (active LOW)
select input
R1, G1, B1, R2, G2, B2
TEST
[1]
SEL
[1]
[2]
Test pin used to enable test mode. For normal usage, this pin must be connected to V
CC(A)
.
Pin can be connected to V
CC(A)
.
7. Functional description
The NX5DV713 integrates high-bandwidth SPDT switches, level-translating buffers and
level translating SPDT switches to provide a complete solution for 1-to-2 switching of VGA
signals. A select input (SEL) is used to determine which output is selected.
7.1 RGB switches
The NX5DV713 provides three identical single pole double throw high-bandwidth switches
to route standard VGA RGB signals (see
Table 3).
Table 3.
Function table RGB
H = HIGH voltage level; L = LOW voltage level; X = Don’t care.
Input
SEL
L
H
R0 to R1; G0 to G1; B0 to B1
R0 to R2; G0 to G2; B0 to B2
Switch
7.2 H-Sync/V-Sync level translator
The horizontal and vertical synchronization buffers have inputs (H0, V0) referenced to
V
CC(A)
and outputs (H1, V1 and H2,V2) that are referenced to V
CC(B)
. This allows level
translation of synchronization signals from as low as 2.0 V up to 5.5 V and supports
low-voltage CMOS or TTL-compatible graphics controllers meeting the VESA
specification for output drive of
8
mA.
Table 4.
Function table HV
H = HIGH voltage level; L = LOW voltage level; X = Don’t care.
Input
SEL
L
H
H1 = H0; V1 = V0; H2, V2 = L
H2 = H0; V2 = V0; H1, V1 = L
Switch
NX5DV713
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 24 November 2011
4 of 20
NXP Semiconductors
NX5DV713
Dual supply 1-of-2 VGA switch
7.3 Display-Data Channel Multiplexer
The NX5DV713 provides two identical SPDT active-level translating switches to route
DDC signals (See
Table 5).
The switch outputs are limited to a diode drop less than the
voltage applied on V
CC(A)
. To provide VESA I
2
C-compatible signals 3.3 V should be
applied to V
CC(A)
. If voltage translation is not required V
CC(A)
should be connected to
V
CC(B)
. Switch terminals include integrated pull-up resistors; inputs (SDA0, SCL0) are
pulled up to V
CC(A)
, outputs (SDA1, SCL1 and SDA2, SCL2) are pulled up to V
CC(B)
.
Table 5.
Function table DDC
H = HIGH voltage level; L = LOW voltage level; X = Don’t care.
Input
SEL
L
H
SDA0 to SDA1, SCL0 to SCL1
SDA0 to SDA2, SCL0 to SCL2
Switch
8. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC(A)
V
CC(B)
V
I
V
SW
I
IK
I
SK
I
OK
I
O
I
CC
I
GND
I
SW
Parameter
supply voltage A
supply voltage B
input voltage
switch voltage
input clamping current
switch clamping current
output clamping current
output current
supply current
ground current
switch current
V
SW
>
0.5
V or V
SW
< 6 V;
source or sink current
V
SW
>
0.5
V or V
SW
< 6 V;
pulsed at 1 ms duration, < 10 % duty cycle;
peak current
T
stg
P
tot
[1]
[2]
[1]
[1]
Conditions
Min
0.5
0.5
0.5
0.5
50
50
50
-
-
100
-
-
Max
+6
+6
+6
+6
-
-
-
50
100
-
30
90
Unit
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
V
I
<
0.5
V
V
I
<
0.5
V
V
O
< 0 V
V
O
= 0 V to V
CC(B)
I
CC(A)
or I
CC(B)
storage temperature
total power dissipation
T
amb
=
40 C
to +85
C
[2]
65
-
+150
250
C
mW
The minimum input voltage rating may be exceeded if the input current rating is observed.
For HWQFN32 package: above 137
C
the value of P
tot
derates linearly with 20.5 mW/K.
NX5DV713
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 24 November 2011
5 of 20
模拟电子
