PHK4NQ20T
N-channel TrenchMOS standard level FET
Rev. 02 — 15 January 2010
Product data sheet
1. Product profile
1.1 General description
Standard level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features and benefits
Low conduction losses due to low
on-state resistance
1.3 Applications
DC-to-DC convertors
General purpose power switching
1.4 Quick reference data
Table 1.
V
DS
I
D
P
tot
Quick reference
Conditions
T
sp
= 25 °C; V
GS
= 10 V;
see
Figure 1
and
3
T
sp
= 25 °C; see
Figure 2
Min
-
-
-
Typ
-
-
-
Max
200
4
6.25
Unit
V
A
W
drain-source voltage T
j
≥
25 °C; T
j
≤
150 °C
drain current
total power
dissipation
drain-source
on-state resistance
Symbol Parameter
Static characteristics
R
DSon
V
GS
= 10 V; I
D
= 4 A;
T
j
= 25 °C;
see
Figure 9
and
10
-
108
130
mΩ
NXP Semiconductors
PHK4NQ20T
N-channel TrenchMOS standard level FET
2. Pinning information
Table 2.
Pin
1
2
3
4
5
6
7
8
S
S
S
G
D
D
D
D
Pinning information
Symbol
Description
source
source
source
gate
drain
drain
drain
drain
1
4
mbb076
Simplified outline
8
5
Graphic symbol
D
G
S
SOT96-1 (SO8)
3. Ordering information
Table 3.
Ordering information
Package
Name
PHK4NQ20T
SO8
Description
plastic small outline package; 8 leads; body width 3.9 mm
Version
SOT96-1
Type number
4. Limiting values
Table 4.
Symbol
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
I
S
I
SM
Limiting values
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
T
sp
= 25 °C
T
sp
25 °C; t
p
≤
10 µs; pulsed
T
sp
= 100 °C; V
GS
= 10 V; see
Figure 1
T
sp
= 25 °C; V
GS
= 10 V; see
Figure 1
and
3
T
sp
= 25 °C; t
p
≤
10 µs; pulsed; see
Figure 3
T
sp
= 25 °C; see
Figure 2
Conditions
T
j
≥
25 °C; T
j
≤
150 °C
T
j
≥
25 °C; T
j
≤
150 °C; R
GS
= 20 kΩ
Min
-
-
-20
-
-
-
-
-55
-55
-
-
Max
200
200
20
2.58
4
16
6.25
150
150
4
16
Unit
V
V
V
A
A
A
W
°C
°C
A
A
In accordance with the Absolute Maximum Rating System (IEC 60134).
Source-drain diode
PHK4NQ20T_2
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 15 January 2010
2 of 13
NXP Semiconductors
PHK4NQ20T
N-channel TrenchMOS standard level FET
120
I
der
(%)
80
03aa25
120
P
der
(%)
80
03aa17
40
40
0
0
50
100
150
T
sp
(°C)
200
0
0
50
100
150
T
sp
(°C)
200
Fig 1.
Normalized continuous drain current as a
function of solder point temperature
Fig 2.
Normalized total power dissipation as a
function of solder point temperature
003aaa234
10
2
I
D
(A)
10
t
p
= 10
μs
1 ms
1
DC
10
−1
1s
10 ms
100 ms
Limit R
DSon
= V
DS
/I
D
10
−2
10
−1
1
10
10
2
V
DS
(V)
10
3
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PHK4NQ20T_2
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 15 January 2010
3 of 13
NXP Semiconductors
PHK4NQ20T
N-channel TrenchMOS standard level FET
5. Thermal characteristics
Table 5.
Symbol
R
th(j-sp)
R
th(j-a)
Thermal characteristics
Parameter
Conditions
Min
-
-
Typ
-
70
Max
20
-
Unit
K/W
K/W
thermal resistance from see
Figure 4
junction to solder point
thermal resistance from minimum footprint; mounted on printed
junction to ambient
circuit-board
10
2
Z
th(j-sp)
(K/W)
10
δ
= 0.5
0.1
0.05
0.02
1
0.01
P
003aaa235
δ
=
t
p
T
10
−1
single pulse
t
p
t
T
10
−2
10
−4
10
−3
10
−2
10
−1
1
t
p
(s)
10
Fig 4.
Transient thermal impedance from junction to ambient as a function of pulse duration
PHK4NQ20T_2
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 15 January 2010
4 of 13
NXP Semiconductors
PHK4NQ20T
N-channel TrenchMOS standard level FET
6. Characteristics
Table 6.
Symbol
V
(BR)DSS
V
GS(th)
Characteristics
Parameter
drain-source
breakdown voltage
gate-source threshold
voltage
Conditions
I
D
= 250 µA; V
GS
= 0 V; T
j
= 25 °C
I
D
= 250 µA; V
GS
= 0 V; T
j
= -55 °C
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 150 °C;
see
Figure 8
I
D
= 1 mA; V
DS
= V
GS
; T
j
= -55 °C;
see
Figure 8
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 25 °C;
see
Figure 8
I
DSS
I
GSS
R
DSon
drain leakage current
gate leakage current
drain-source on-state
resistance
V
DS
= 160 V; V
GS
= 0 V; T
j
= 25 °C
V
DS
= 160 V; V
GS
= 0 V; T
j
= 150 °C
V
GS
= 10 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= -10 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= 10 V; I
D
= 4 A; T
j
= 150 °C;
see
Figure 9
and
10
V
GS
= 5 V; I
D
= 3 A; T
j
= 25 °C
V
GS
= 10 V; I
D
= 4 A; T
j
= 25 °C;
see
Figure 9
and
10
Dynamic characteristics
Q
G(tot)
Q
GS
Q
GD
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
V
SD
t
rr
Q
r
total gate charge
gate-source charge
gate-drain charge
input capacitance
output capacitance
reverse transfer
capacitance
turn-on delay time
rise time
turn-off delay time
fall time
source-drain voltage
reverse recovery time
recovered charge
I
S
= 4 A; V
GS
= 0 V; T
j
= 25 °C;
see
Figure 13
I
S
= 4 A; dI
S
/dt = -100 A/µs; V
GS
= 0 V;
V
DS
= 120 V; T
j
= 25 °C
V
DS
= 100 V; R
L
= 25
Ω;
V
GS
= 10 V;
R
G(ext)
= 6
Ω;
T
j
= 25 °C
V
DS
= 25 V; V
GS
= 0 V; f = 1 MHz;
T
j
= 25 °C; see
Figure 12
I
D
= 4 A; V
DS
= 100 V; V
GS
= 10 V;
T
j
= 25 °C; see
Figure 11
-
-
-
-
-
-
-
-
-
-
-
-
-
26
4
8.7
1230
155
48
13
10
35
14
0.81
245
104
-
-
-
-
-
-
-
-
-
-
1.2
-
-
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
V
ns
nC
Min
200
178
1.2
-
2
-
-
-
-
-
-
-
Typ
-
-
-
-
3
-
-
10
10
260
110
108
Max
-
-
-
4.5
4
1
100
100
100
312
150
130
Unit
V
V
V
V
V
µA
µA
nA
nA
mΩ
mΩ
mΩ
Static characteristics
Source-drain diode
PHK4NQ20T_2
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 15 January 2010
5 of 13
