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ONET1130EC
SLLSEJ3A – JUNE 2015 – REVISED JULY 2015
ONET1130EC 11.7 Gbps Transceiver with Dual CDRs and Modulator Driver
1 Features
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Dual CDR with 9.80-11.7 Gbps Reference-Free
Operation
2-Wire Digital Interface with Integrated DACs and
ADC for Control and Diagnostic Management
Output Polarity Select for TX and RX
Programmable Jitter Transfer Bandwidth
Electrical and Optical Loopback.
CDR Bypass Mode for Low Data Rate Operation
Integrated Modulator Driver with Output Amplitude
up to 2 V
PP
Single-ended and Bias Current up to
150 mA Source.
Automatic Power Control (APC) Loop with
Selectable Monitor PD Range
Programmable TX Input Equalizer
TX Cross-Point Adjust and De-Emphasis
Includes Laser Safety Features
Integrated Limiting Amplifier with Programmable
LOS Threshold
Adjustable RX Equalization and Input Threshold
Programmable RX Output Voltage and De-
emphasis.
Power Supply Monitor and Temperature Sensor
Single 2.5-V Supply
–40°C to 100°C Operation
Surface Mount 4 mm x 4 mm 32-Pin QFN
Package with 0.4 mm Pitch
The transmit path consists of an adjustable input
equalizer for equalization of up to 300 mm
(12 inches) of microstrip or stripline transmission line
of FR4 printed circuit boards, a multi-rate CDR and
an output modulator driver. Output waveform control,
in the form of cross-point adjustment and de-
emphasis are available to improve the optical eye
mask margin. Bias current for the laser is provided
and an integrated automatic power control (APC) loop
to compensate for variations in average optical power
over voltage, temperature and time is included.
The receive path consists of a limiting amplifier with
programmable equalization and threshold adjustment,
a multi-rate CDR and output de-emphasis to
compensate for frequency dependent loss of
connectors, microstrips or striplines connected to the
output of the device, The receiver output amplitude
and loss of signal assert level can be adjusted.
Device Information
ORDER NUMBER
ONET1130EC
PACKAGE (PIN)
VQFN (32)
BODY SIZE
4.00 mm x 4.00 mm
Simplified Schematic
VCC
VCC_T
4.7k
to10k
4.7k
to10k
0.1 F
0.1 F
4.7k
to10k
RXOUT-
RXOUT+
2.2nF
TX_FLT
TX_DIS
VCC_RX
TX_DIS
RXOUT+
TX_FLT
RXOUT-
VCC_RX
VCC_RX
RX_DIS
RX_LF
0.1 F
0.1 F
VCC_R
4.7k
to10k
2 Applications
•
•
XFP and SFP+ 10 Gbps SONET OC-192 Optical
Transceivers
XFP and SFP+ 10 GBASE-ER/ZR Optical
Transceivers
LOL
MONB
0.1 F
LOL
MONB
GND
TXIN+
RX_LOS
0.01 F
COMP
GND
0.1 F
RXIN-
LOS
TXIN+
TXIN-
0.1 F
PD
RXIN-
RXIN+
0.1 F
ONET1130EC
TXIN-
GND
PD
TXOUT-
MONP
TX_LF
BIAS
TXOUT+
VCC_TX
VCC_TX
RXIN+
GND
SCK
SDA
VDD
AMP
4.7k
to10k
SCK
SDA
4.7k
to10k
3 Description
The ONET1130EC is a 2.5 V integrated modulator
driver and limiting amplifier with transmit and receive
clock and data recovery (CDR) designed to operate
between 9.80 Gbps and 11.7 Gbps without the need
for a reference clock. Optical and electrical loopback
are included. CDR bypass mode can be used for
operation at lower data rates and a two-wire serial
interface allows digital control of the features.
MONP
VCC
VCC_TX
0.1 F
Modulator Anode
2.2nF
0.1 F
0.1 F
VDD
0.1 F
50
Laser
EA BIAS
PD
PD
EML TOSA
0.1 F
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ONET1130EC
SLLSEJ3A – JUNE 2015 – REVISED JULY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features
..................................................................
Applications
...........................................................
Description
.............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Function
...........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
1
1
1
2
3
3
5
8.2
8.3
8.4
8.5
8.6
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming ..........................................................
Register Mapping ....................................................
20
21
31
31
32
9
Application Information and Implementations
.
49
9.1 Application Information............................................
49
9.2 Typical Application, Transmitter Differential Mode..
49
Absolute Maximum Ratings .....................................
5
ESD Ratings ............................................................
5
Recommended Operating Conditions.......................
5
Thermal Information ..................................................
6
DC Electrical Characteristics ....................................
6
Transmitter AC Electrical Characteristics .................
8
Receiver AC Electrical Characteristics .....................
9
Timing Requirements ..............................................
10
Typical Characteristics ............................................
13
10 Power Supply Recommendations
.....................
53
11 Layout...................................................................
54
11.1 Layout Guidelines .................................................
54
11.2 Layout Example ....................................................
54
12 Device and Documentation Support
.................
55
12.1
12.2
12.3
12.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
55
55
55
55
8
Detailed Description
............................................
19
8.1 Overview .................................................................
19
13 Mechanical, Packaging, and Orderable
Information
...........................................................
55
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (June 2015) to Revision A
•
Page
Changed From: Product Preview To Production ...................................................................................................................
1
2
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Copyright © 2015, Texas Instruments Incorporated
ONET1130EC
www.ti.com
SLLSEJ3A – JUNE 2015 – REVISED JULY 2015
5 Description (continued)
The ONET1130EC contains internal analog to digital and digital to analog converters to support transceiver
management and eliminate the need for special purpose microcontrollers.
The transceiver is characterized for operation from –40°C to 100°C case temperatures and is available in a small
footprint 4mm × 4mm, 32 pin RoHS compliant VQFN package.
6 Pin Configuration and Function
RSM PACKAGE
32 PIN VQFN
(TOP VIEW)
RXOUT+
VCC_RX
VCC_RX
RXOUT±
RX_DIS
26
TX_FLT
TX_DIS
RX_LF
25
24
23
22
21
20
19
EP
18
17
9
TX_LF
10
BIAS
11
VCC_TX
12
TXOUT±
13
TXOUT+
14
VCC_TX
15
VDD
16
AMP
RX_LOS
COMP
GND
RXIN±
RXIN+
GND
SCK
SDA
32
LOL
MONB
GND
TXIN+
TXIN±
GND
PD
MONP
1
2
3
4
5
6
7
8
31
30
29
28
27
Pin Functions
NUMBER
AMP
BIAS
COMP
GND
LOL
MONB
MONP
PD
RX_DIS
RX_LF
RX_LOS
RXIN+
RXIN-
RXOUT–
RXOUT+
NAME
16
10
23
3, 6, 19, 22
1
2
8
7
26
25
24
20
21
28
29
Type
Analog-in
Analog
Analog
Supply
Digital-out
Analog-out
Analog-out
Analog
Digital-in
Analog-in
Digital-out
Analog-in
Analog-in
CML-out
CML-out
DESCRIPTION
Output amplitude control. Output amplitude can be adjusted by applying a voltage of
0 to 2 V to this pin. Leave open when not used.
Sinks or sources the bias current for the laser in both APC and open loop modes.
Compensation pin used to control the bandwidth of the APC loop. Connect a 0.01-µF
capacitor to ground.
Circuit ground.
Transmitter and receiver loss of lock indicator. High level indicates the transmitter or
the receiver is out of lock. Open drain output. Requires an external 4.7 kΩ to 10 kΩ
pull-up resistor to VCC for proper operation. This pin is 3.3 V tolerant.
Bias current monitor.
Photodiode current monitor.
Photodiode input. Pin can source or sink current dependent on register setting.
Disables the receiver output buffer when set to a high level. Includes a 250-kΩ pull-
up resistor to VCC. Ground the pin to enable the output. This is an ORed function
with the RXOUT_DIS bit (bit 6 in
register 4).
This pin is 3.3-V tolerant.
Receiver loop filter capacitor.
Receiver loss of signal. High level indicates that the receiver input signal amplitude is
below the programmed threshold level. Open drain output. Requires an external 4.7-
kΩ to 10-kΩ pull-up resistor to VCC for proper operation. This pin is 3.3-V tolerant.
Non-inverted receiver data input. On-chip differentially 100
Ω
terminated to RXIN–.
Must be AC coupled.
Inverted receiver data input. On-chip differentially 100
Ω
terminated to RXIN+. Must
be AC coupled.
Inverted receiver data output. 45
Ω
back-terminated to VCC.
Non-inverted data output. 45
Ω
back-terminated to VCC.
Copyright © 2015, Texas Instruments Incorporated
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ONET1130EC
SLLSEJ3A – JUNE 2015 – REVISED JULY 2015
www.ti.com
Pin Functions (continued)
NUMBER
SDA
SCK
NAME
17
18
Type
Digital-in/out
Digital-in
DESCRIPTION
2-wire interface serial data input. Requires an external 4.7-kΩ to10-kΩ pull-up resistor
to VCC. This pin is 3.3-V tolerant.
2-wire interface serial clock input. Requires an external 4.7-kΩ to10-kΩ pull-up
resistor to VCC. This pin is 3.3-V tolerant.
Disables both bias and modulation currents when set to high state. Includes a 250-kΩ
pull-up resistor to VCC. Requires an external 4.7 kΩ to 10 kΩ pull-up resistor to VCC
for proper operation Toggle to reset a fault condition. This is an ORed function with
the TXBIASEN bit (bit 2 in
register 1).
This pin is 3.3-V tolerant.
Non-inverted transmitter data input. On-chip differentially 100
Ω
terminated to TXIN–.
Must be AC coupled.
Inverted transmitter data input. On-chip differentially 100
Ω
terminated to TXIN+. Must
be AC coupled.
Transmitter loop filter capacitor.
Transmitter fault detection flag. High level indicates that a fault has occurred. Open
drain output. Requires an external 4.7 kΩ to 10 kΩ pull-up resistor to VCC for proper
operation. This pin is 3.3-V tolerant.
Inverted transmitter data output. Internally terminated in single-ended operation
mode.
Non-Inverted transmitter data output.
2.5 V ± 5% supply for the receiver.
2.5 V ± 5% supply for the transmitter.
2.5 V ± 5% supply for the digital circuitry.
Exposed die pad. Solder to the PCB.
TX_DIS
32
Digital-in
TXIN+
TXIN–
TX_LF
TX_FLT
TXOUT–
TXOUT+
VCC_RX
VCC_TX
VDD
Exposed Pad
4
5
9
31
12
13
27, 30
11, 14
15
EP
Analog-in
Analog-in
Analog-in
Digital-out
CML-out
CML-out
Supply
Supply
Supply
4
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Copyright © 2015, Texas Instruments Incorporated
ONET1130EC
www.ti.com
SLLSEJ3A – JUNE 2015 – REVISED JULY 2015
7 Specifications
7.1 Absolute Maximum Ratings
(1) (2)
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage
at VCC_TX, VCC_RX, VDD
at 3.3-V tolerant pins LOL, SDA, SCK, RX_LOS, RX_DIS,
TX_FLT, TX_DIS
Voltage
at all other pins MONB, TXIN+, TXIN–, PD, MONP, TX_LF,
BIAS, TXOUT–, TXOUT+, AMP, RXIN+, RXIN–, COMP,
RX_LF, RXOUT–, RXOUT+,
–0.5
–0.5
–0.5
MAX
3
3.6
3
10
125
10
30
125
–65
150
UNIT
V
V
V
mA
mA
mA
mA
°C
°C
Maximum current at transmitter input pins TXIN+, TXIN–
Maximum current at transmitter output
pins
Maximum current at receiver input pins
Maximum current at receiver output pins
Maximum junction temperature, T
J
Storage temperature, T
stg
(1)
(2)
TXOUT+, TXOUT–
RXIN+, RXIN–
RXOUT+, RXOUT–
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
7.2 ESD Ratings
VALUE
V
(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
V
±2000
±750
Charged-device model (CDM), per JEDEC specification JESD22-C101
(2)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
V
CC
V
IH
V
IL
Supply Voltage
Digital input high voltage
Digital input low voltage
Photodiode current range
TX_DIS, RX_DIS, SCK, SDA, 3.3-V tolerant IOs
Control bit TXPDRNG = 1x, step size = 3 µA
Control bit TXPDRNG = 01, step size = 1.5 µA
Control bit TXPDRNG = 00, step size = 0.75 µA
Serial Data rate
V
AMP
t
R-IN
t
F-IN
T
C
TXCDR_DIS = 0 and RXCDR_DIS = 0
TXCDR_DIS = 1 and RXCDR_DIS = 1
20%–80%
20%–80%
–40
9.8
1
0
30
30
2.37
2
0.8
3080
1540
770
11.7
11.7
2
45
45
100
Gbps
V
ps
ps
°C
µA
TYP
2.5
MAX
2.63
UNIT
V
V
V
Amplitude control input voltage range
Input rise time
Input fall time
Temperature at thermal pad
Copyright © 2015, Texas Instruments Incorporated
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ONET1130EC
5
