ONET1141L
www.ti.com
SLLSEB7 – MAY 2012
11.3 Gbps Modulator Driver
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ONET1141L
1
FEATURES
Digitally Selectable Output Amplitude up to
2.0VPP Single-Ended
Digitally Selectable Bias Current up to 145mA
Source
2-wire Digital Interface with Integrated DACs
and ADC for Control and Diagnostic
Management
Automatic Power Control (APC) Loop
Adjustable Rise and Fall Times
Programmable Input Equalizer
Cross-Point Control
Selectable Monitor PD Current Range and
Polarity
•
•
•
•
•
•
•
Includes Laser Safety Features
Single 3.3V Supply
–40°C to 100°C Operation
Surface Mount Small Footprint 4mm × 4mm 24
Pin RoHS Compliant QFN Package
APPLICATIONS
•
•
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10 Gigabit Ethernet Optical Transmitters
SONET OC-192/SDH STM-64 Optical
Transmitters
10G-EPON and XG-PON
SFP+ and XFP Transceiver Modules
XENPAK, XPAK, X2 and 300-pin MSA
Transponder Modules
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DESCRIPTION
The ONET1141L is a high-speed, 3.3V electroabsorption modulator driver designed to bias and modulate an
electroabsorptive modulated laser (EML) at data rates from 1 Gbps up to 11.3 Gbps.
The device provides a two-wire serial interface which allows digital control of the modulation and bias currents,
eliminating the need for external components. Output waveform control, in the form of cross-point adjustment
and rise and fall time adjustment are available to improve the optical eye mask margin. An optional input
equalizer can be used for equalization of up to 150mm (6”) of microstrip or stripline transmission line on FR4
printed circuit boards. The device contains internal analog to digital and digital to analog converters to eliminate
the need for special purpose microcontrollers.
The ONET1141L includes an integrated automatic power control (APC) loop which compensates for variations in
laser average optical power over voltage and temperature and circuitry to support laser safety and transceiver
management systems.
The modulator driver is characterized for operation from –40°C to 100°C case temperatures and is available in a
small footprint 4mm × 4mm 24 pin RoHS compliant QFN package.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
ONET1141L
SLLSEB7 – MAY 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
BLOCK DIAGRAM
A simplified block diagram of the ONET1141L is shown in
Figure 1.
The modulator driver consists of an input
equalizer with selectable bypass, a limiter, an output driver, DC offset cancellation with cross point control,
power-on reset circuitry, a 2-wire serial interface including a control logic block, a modulation current generator, a
bias current generator with automatic power control loop, an analog to digital converter and an analog reference
block.
VCCO
VCC
To all Blocks Except Output Driver
Crosspoint
Adjust
DC Offset Cancellation
60Ω
60Ω
OUT+
100Ω
DIN+
DIN-
Equalizer
Amplifier
+
+
Bypass
OUT-
Limiter
VCC
Mod.
Current
Generator
Adjustable
Boost
10kΩ
10kΩ
10kΩ
8 Bit Register
8 Bit Register
SDA
SCK
DIS
10 Bit Register
10 Bit Register
8 Bit Register
8 Bit Register
5 Bit Register
8 Bit Register
3 Bit Register
8 Bit Register
8 Bit Register
Settings
Settings
IMOD
IBIAS
Equalizer
Crosspoint
Crosspoint Settings
Limiter Current
Monitor Settings
Bias Current Fault
PD Current Fault
ADC Settings
ADC
Power-On
Reset
SDA
SCK
DIS
Crosspoint Adjust
BIAS
Bias
Current
MONB
Generator/
MONP
Monitor &
FLT
APC
MONB
MONP
PD
COMP
BIAS
MONB
MONP
FLT
PD
COMP
Analog to
Digital
Conversion
ADR0
ADR1
ADR1
8 Bit Register
10 Bit Register
ADR2
2-Wire Interface & Control Logic
Band-Gap, Analog References,
Power supply Monitor &
Temperature Sensor
PSM
TS
RZTC
RZTC
Figure 1. Simplified Block Diagram of the ONET1141L
PACKAGE
The ONET1141L is packaged in a small footprint 4mm X 4mm 24 pin RoHS compliant QFN package with a lead
pitch of 0.5mm. The pin out is shown below.
2
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Copyright © 2012, Texas Instruments Incorporated
ONET1141L
www.ti.com
SLLSEB7 – MAY 2012
24 PIN QFN PACKAGE, 4mm x 4mm
(TOP VIEW)
VCCO
GND
OUT+
24 23 22 21 20 19
PD
1
ADR0
2
ONET 1101L
ONET 1141L
VCCO
18
BIAS
17
GND
16
VCC
15
COMP
14
MONP
13
MONB
OUT-
ADR1
3
DIS
4
SCK
5
SDA
6
7
24 Lead QFN
24 Lead QFN
“ RGE
”
8
9 10 11 12
DIN+
DIN -
GND
GND
PIN FUNCTIONS
NO.
PIN
1
2
3
4
5
6
7
NAME
PD
ADR0
ADR1
DIS
SCK
SDA
FLT
TYPE
Analog
Digital-in
Digital-in
Digital-in
Digital-in
Digital-in/out
Digital-out
Supply
Analog-in
Analog-in
Analog
Analog-out
DESCRIPTION
Photodiode input. Pin can source or sink current dependent on register setting.
2-wire interface address programming pin. Leave this pad open for a default address of 0001000.
Pulling the pin to VCC changes the 1
st
address bit to a 1 (address = 0001001)
2-wire interface address programming pin. Leave this pad open for a default address of 0001000.
Pulling the pin to VCC changes the 2
nd
address bit to a 1 (address = 0001010)
Disables both bias and modulation currents when set to high state. Includes a 10kΩ or 40kΩ pull-up
resistor to VCC. Toggle to reset a fault condition.
2-wire interface serial clock input. Includes a 10kΩ or 40kΩ pull-up resistor to VCC.
2-wire interface serial data input/output. Includes a 10kΩ or 40kΩ pull-up resistor to VCC.
Fault detection flag. High level indicates that a fault has occurred. Open drain output. Requires an
external 4.7kΩ to 10kΩ pull-up resistor to VCC for proper operation.
Circuit ground. Exposed die pad (EP) must be grounded.
Non-inverted data input. On-chip differentially 100Ω terminated to DIN–. Must be AC coupled.
Inverted data input. On-chip differentially 100Ω terminated to DIN+. Must be AC coupled.
Connect external zero TC 28.7kΩ resistor to ground (GND). Used to generate a defined zero TC
reference current for internal DACs.
Bias current monitor. Sources a 1% replica of the bias current. Connect an external resistor to
ground (GND) to use the analog monitor (DMONB = 0). If the voltage at this pin exceeds 1.16V a
fault is triggered. Typically choose a resistor to give MONB voltage of 0.8V at the maximum desired
bias current. If the digital monitor function is used (DMONB = 1) the resistor must be removed.
Photodiode current monitor. Sources a 12.5% replica of the photodiode current when PDRNG = 1X,
a 25% replica when PDRNG = 01 and a 50% replica when PDRNG = 00. Connect an external
resistor (5kΩ typical) to ground (GND) to use the analog monitor (DMONP = 0). If the voltage at this
pin exceeds 1.16V a fault is triggered when MONPFLT = 1. If the digital monitor function is used
(DMONP = 1) the resistor must be removed.
Compensation pin used to control the bandwidth of the APC loop. Connect a 0.01µF capacitor to
ground.
3.3V ± 10% supply voltage.
Sinks or sources the bias current for the laser in both APC and open loop modes.
3.3V ± 10% supply voltage for the output stage.
Inverted data output.
Non-inverted data output.
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3
8, 11, 17, GND
20, 23, EP
9
10
12
13
DIN+
DIN–
RZTC
MONB
14
MONP
Analog-out
15
16
18
19, 24
21
22
COMP
VCC
BIAS
VCCO
OUT–
OUT+
Analog
Supply
Analog
Supply
CML-out
CML-out
Copyright © 2012, Texas Instruments Incorporated
RZTC
GND
FLT
ONET1141L
SLLSEB7 – MAY 2012
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE
MIN
V
CC
V
ADR0
, V
ADR1
, V
DIS
, V
RZTC
,
V
SCK
, V
SDA
, V
DIN+
, V
DIN-
, V
FLT
,
V
MONB
, V
MONP
, V
COMP
, V
PD
,
V
BIAS
, V
OUT+
, V
OUT-
I
DIN-
, I
DIN+
I
OUT+
, I
OUT–
I
BIAS-MAX
ESD
T
J,max
T
STG
T
C
(1)
(2)
Supply voltage
(2)
UNIT
4.0
4.0
25
120
180
2
125
V
V
mA
mA
mA
kV (HBM)
°C
°C
°C
MAX
–0.3
–0.3
Voltage at ADR0, ADR1, DIS, RZTC, SCK, SDA, DIN+, DIN–, FLT, MONB,
MONP, COMP, PD, BIAS, OUT+, OUT–
(2)
Maximum current at input pins
Maximum current at output pins
Maximum bias current
ESD rating at all pins
Maximum junction temperature
Storage temperature range
Case temperature
–65
–40
150
110
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
V
CC
V
IH
V
IL
Supply voltage
Digital input high voltage
Digital input low voltage
Photodiode current range
R
RZTC
v
IN
t
R-IN
t
F-IN
T
C
(1)
Zero TC resistor value
(1)
Differential input voltage swing
Input rise time
Input fall time
Temperature at thermal pad
Changing the value will alter the DAC ranges.
DIS, SCK, SDA
DIS, SCK, SDA
Control bit PDRNG = 1X,step size = 3 µA
Control bit PDRNG = 01,step size = 1.5 µA
Control bit PDRNG = 00,step size = 0.75 µA
1.16V bandgap bias acrossresistor, E96, 1% accuracy
EQENA = 1
EQENA = 0
20%–80%
20%–80%
-40
28.4
160
400
30
30
3080
1540
770
28.7
29
1000
1000
55
55
100
kΩ
mV
p-p
ps
ps
°C
µA
2.97
2.0
0.8
TYP
3.3
MAX
3.63
UNIT
V
V
V
4
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Copyright © 2012, Texas Instruments Incorporated
ONET1141L
www.ti.com
SLLSEB7 – MAY 2012
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions, with 50Ω output load, open loop operation, V
OUT
= 2.0Vpp, I
BIAS
= 80 mA, and R
RZTC
= 28.7kΩ unless otherwise noted. Typical operating condition is at V
CC
=3.3V and T
A
= 25°C
PARAMETER
V
CC
Supply voltage
V
OUT
= 2.0Vpp, I
BIAS
= 0mA, EQENA = 0
I
VCC
Supply current
V
OUT
= 2.0Vpp, I
BIAS
= 0mA, EQENA = 1
Output off (DIS = HIGH), V
OUT
= 2.0Vpp,
I
BIAS
= 80 mA, EQENA = 0
Data input resistance
Output resistance
Digital input current
Digital input current
V
OH
V
OL
I
BIAS-MIN
Digital output high voltage
Digital output low voltage
Minimum bias current
Differential between DIN+ / DIN–
Single-ended at OUT+ or OUT–
SCK, SDA, pull up to VCC
DIS, pull up to VCC
FLT, pull-up to V
CC
, I
SOURCE
= 50 µA
FLT, pull-up to V
CC
, I
SINK
= 350 µA
See
(1)
CONDITION
MIN
2.97
TYP
3.3
143
151
40
MAX
3.63
170
182
UNIT
V
mA
R
IN
R
OUT
82
50
2
2
2.4
100
60
360
360
118
70
470
470
0.4
5
Ω
Ω
µA
µA
V
V
mA
I
BIAS-MAX
Maximum bias current
Source. BIASPOL = 0, DAC set to maximum, open
and closed loop
Sink. BIASPOL = 1, DAC set to maximum, open and
closed loop
APC loop enabled
Source. BIASPOL = 0
Sink. BIASPOL = 1
With 1-point external mid scale calibration
APC active, I
PD
= max
Percent of target I
PD (2)
I
MONP
/ I
PD
with control bit PDRNG = 1X
145
93
160
mA
105
100
±0.5
µA
dB
V
V
CC
–0.9
±3
°C
V
I
BIAS-DIS
Bias current during disable
Average power stability
Bias pin compliance voltage
Temperature sensor accuracy
0.9
V
PD
Photodiode reverse bias
voltage
Photodiode fault current level
Photodiode current monitor
ratio
Monitor diode DMI accuracy
Bias current monitor ratio
Bias current DMI accuracy
Power supply monitor
accuracy
1.3
2.3
150%
10%
20%
40%
-10%
0.9%
12.5%
25%
50%
1.0%
±10%
15%
30%
60%
10%
1.1%
I
MONP
/ I
PD
with control bit PDRNG = 01
I
MONP
/ I
PD
with control bit PDRNG = 00
With external calibration at 200 µA
I
MONB
/ I
BIAS
(nominal 1/100 = 1%)
Bias current
≥
30 mA
With external mid scale calibration
V
CC
voltage level which triggers power-on reset
–2%
2.5
100
2%
2.8
V
mV
1.24
V
V
CC-RST
V
CC-RSTHYS
V
MONB-FLT
(1)
(2)
V
CC
reset threshold voltage
V
CC
reset threshold voltage
hysteresis
Fault voltage at MONB
Fault occurs if voltage at MONB exceeds value
1.1
1.16
The bias current can be set below the specified minimum according to the corresponding register setting, however in closed loop
operation settings below the specified value may trigger a fault.
Assured by simulation over process, supply and temperature variation.
Copyright © 2012, Texas Instruments Incorporated
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