ONET1151P
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SLLSEH8 – SEPTEMBER 2013
11.3 Gbps Limiting Amplifier
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ONET1151P
1
FEATURES
Up to 11.3 Gbps Operation
Two-Wire Digital Interface
Adjustable LOS Threshold
Digitally Selectable Output Voltage
Digitally Selectable Output De-Emphasis
Adjustable Input Threshold Voltage
Output Polarity Select
Programmable LOS Masking Time
Input Offset Cancellation
CML Data Outputs with On-Chip 50-Ω Back-
Termination to VCC
Single +3.3-V Supply
Low Power Consumption
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Output Disable
Surface Mount Small Footprint 3 mm × 3 mm
16-Pin RoHS Compliant QFN Package
Pin Compatible to the ONET8501PB
APPLICATIONS
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10 Gigabit Ethernet Optical Receivers
2x/4x/8x and 10x Fibre Channel Optical
Receivers
SONET OC-192/SDH-64 Optical Receivers
SFP+ and XFP Transceiver Modules
Cable Driver and Receiver
DESCRIPTION
The ONET1151P is a high-speed, 3.3-V limiting amplifier for multiple fiber optic and copper cable applications
with data rates up to 11.3 Gbps.
The device provides a two-wire serial interface which allows digital control of the output amplitude, output pre-
emphasis, input threshold voltage (slice level) and the loss of signal assert level.
The ONET1151P provides a gain of about 33dB which ensures a fully differential output swing for input signals
as low as 20 mV
p-p
. The output amplitude can be adjusted between 350 mV
p-p
and 850 mV
p-p
. To compensate for
frequency dependent loss of microstrips or striplines connected to the output of the device, programmable de-
emphasis is included in the output stage. A settable loss of signal (LOS) detection with programmable output
masking time and output disable are also provided.
The part, available in RoHS compliant small footprint 3 mm x 3 mm 16-pin QFN package, typically dissipates 132
mW with 550 mV
p-p
output and is characterized for operation from
−40°C
to 100°C.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
ONET1151P
SLLSEH8 – SEPTEMBER 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
BLOCK DIAGRAM
A simplified block diagram of the ONET1151P is shown in
Figure 1.
This compact, low power 11.3 Gbps limiting amplifier consists of a high-speed data path with offset cancellation
block (DC feedback) combined with an analog settable input threshold adjust, a loss of signal detection block
using 2 peak detectors, a two-wire interface with a control-logic block and a bandgap voltage reference and bias
current generation block.
COC1
COC2
VCC
GND
Offset
Cancellation
VCC
Input
Buffer
Gain Stage
Gain Stage
Output
Buffer
50
50
DIN+
100
DOUT+
DOUT-
LOS
DIN-
LOS Detection
SDA
SCK
DIS
SDA
SCK
DIS
8 Bit Register
8 Bit Register
4 Bit
4 Bit
3 Bit
8 Bit Register
8 Bit Register
8 Bit Register
8 Bit Register
Settings
Input Threshold
CPRNG and DE
Amplitude
Settings
LOS Adjust
LOS Masking
LOS Masking
Power-On
Reset
2-Wire Interface &
Control Logic
Bandgap Voltage
Reference and
Bias Current
Generation
Figure 1. Simplified Block Diagram of the ONET1151P
2
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ONET1151P
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ONET1151P
www.ti.com
SLLSEH8 – SEPTEMBER 2013
PACKAGE
The ONET1151P is available in a small footprint 3 mm × 3 mm 16-pin RoHS compliant QFN package with a lead
pitch of 0.5 mm. The pinout is shown in
Figure 2.
SDA
SCK
16
15
14
NC
13
GND
1
DIN+
2
DIN-
3
GND
4
NC
12
VCC
ONET
1151P
16 Pin QFN
11
DOUT+
10
DOUT-
9
VCC
5
COC1
6
COC2
7
DIS
8
LOS
DESCRIPTION
Figure 2. Pinout of ONET1151P in a 3mm x 3mm 16-Pin QFN Package (Top View)
Table 1. PIN DESCRIPTIONS
PIN
NAME
GND
DIN+
DIN–
COC1
NO.
1, 4, EP
2
3
5
TYPE
Supply
Analog-input
Analog-input
Analog
Circuit ground. Exposed die pad (EP) must be grounded.
Non-inverted data input. Differentially 100
Ω
terminated to DIN–.
Inverted data input. Differentially 100
Ω
terminated to DIN+.
Offset cancellation filter capacitor plus terminal. An external capacitor can be connected
between this pin and COC2 to reduce the low frequency cutoff. To disable the offset
cancellation loop, connect COC1 and COC2 together.
Offset cancellation filter capacitor minus terminal. An external capacitor can be connected
between this pin and COC1 to reduce the low frequency cutoff. To disable the offset
cancellation loop, connect COC1 and COC2 together.
Disables the output stage when set to a high level.
High level indicates that the input signal amplitude is below the programmed threshold level.
Open drain output. Requires an external 10kΩ pull-up resistor to VCC for proper operation.
3.3-V supply voltage.
Inverted data output. On-chip 50
Ω
back-terminated to VCC.
Non-inverted data output. On-chip 50
Ω
back-terminated to VCC.
Do not connect
Serial interface clock input. Connect a pull-up resistor (10 kΩ typical) to VCC.
Serial interface data input. Connect a pull-up resistor (10 kΩ typical) to VCC.
COC2
DIS
LOS
VCC
DOUT–
DOUT+
NC
SCK
SDA
6
7
8
9, 12
10
11
13, 14
15
16
Analog
Digital-input
Open drain
MOS
Supply
CML-out
CML-out
No Connect
Digital-input
Digital-input
Copyright © 2013, Texas Instruments Incorporated
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ONET1151P
SLLSEH8 – SEPTEMBER 2013
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ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
V
CC
V
DIN+
, V
DIN–
V
LOS
, V
COC1
, V
COC2
,
V
DOUT+
, V
DOUT–
, V
DIS
,
V
SDA
, V
SCK
V
DIN,
DIFF
VALUE
MIN
–0.3
0.5
–0.3
MAX
4
4
4.0
±2.5
25
2
–40
–65
–40
100
125
150
110
260
UNIT
V
V
V
V
mA
kV (HBM)
°C
°C
°C
°C
°C
Supply voltage
(2)
Voltage at DIN+, DIN–
(2)
Voltage at LOS, COC1, COC2, DOUT+, DOUT-, DIS, SDA, SCK
(2)
Differential voltage between DIN+ and DIN–
Continuous current at inputs and outputs
ESD rating at all pins
Characterized free-air operating temperature range
Maximum junction temperature
Storage temperature range
Case temperature
Lead temperature 1.6mm (1/16 inch) from case for 10 seconds
I
DIN+
, I
DIN–
, I
DOUT+
,
I
DOUT–
ESD
T
A
T
J, max
T
STG
T
C
T
LEAD
(1)
(2)
Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating
Conditions
is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
V
CC
T
A
Supply voltage
Operating free-air temperature
DIGITAL input high voltage
DIGITAL input low voltage
TEST CONDITIONS
T
A
= –40°C to +100°C
T
A
= –30°C to +100°C
VALUE
MIN
2.9
2.85
–40
2.0
0.8
TYP
3.3
3.3
MAX
3.63
3.63
100
UNIT
V
°C
V
V
DC ELECTRICAL CHARACTERISTICS
over recommended operating conditions with 50-Ω output load, 550 mV
p-p
output voltage and BIAS bit (Register 7) set to 1,
unless otherwise noted. Typical operating condition is at 3.3 V and T
A
= 25°C
PARAMETER
V
CC
I
VCC
R
IN
R
OUT
Supply voltage
Supply current
Data input resistance
Data output resistance
LOS HIGH voltage
LOS LOW voltage
TEST CONDITIONS
T
A
= –40°C to +100°C
T
A
= –30°C to +100°C
DIS = 0, CML currents included
Differential
Single-ended, referenced to V
CC
I
SOURCE
= 50 µA with 10 kΩ pull-up to V
CC
I
SINK
= 10 mA with 10 kΩ pull-up to V
CC
2.3
0.4
VALUE
MIN
2.9
2.85
TYP
3.3
3.3
40
100
50
MAX
3.63
3.63
52
UNIT
V
mA
Ω
Ω
V
V
4
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ONET1151P
www.ti.com
SLLSEH8 – SEPTEMBER 2013
AC ELECTRICAL CHARACTERISTICS
over recommended operating conditions with 50-Ω output load, 550mVpp output voltage and BIAS bit (Register 7) set to 1,
unless otherwise noted. Typical operating condition is at V
CC
= 3.3 V and T
A
= 25°C.
PARAMETER
f3dB-H
f3dB-L
V
IN,MIN
SDD11
SDD22
SCD11
SCC22
A
V
IN-MAX
DJ
RJ
V
OD
V
PREEM
t
R
t
F
CMOV
V
TH
V
TH
-3dB bandwidth default settings
Low frequency -3dB bandwidth
Data input sensitivity
Differential input return gain
Differential output return gain
Differential to common mode conversion gain
Common mode output return gain
Small signal gain
Data input overload
Deterministic jitter at 11.3 Gbps
Random jitter
Differential data output voltage
Output de-emphasis step size
Output rise time
Output fall time
AC common mode output voltage
LOW LOS assert threshold range min.
LOW LOS assert threshold range max.
HIGH LOS assert threshold range min.
HIGH LOS assert threshold range max.
LOS threshold variation
LOS hysteresis (electrical)
T
LOS_AST
LOS assert time
Maximum LOS output masking time
LOS masking time step size
T
DIS
Disable response time
T
LOS_DEA
LOS deassert time
20% – 80%, V
IN
> 30 mV
p-p
20% – 80%, V
IN
> 30 mV
p-p
PRBS31 pattern; AMP[0..2] = 010
K28.5 pattern at 11.3 Gbps, LOSRNG = 0
K28.5 pattern at 11.3 Gbps, LOSRNG = 0
K28.5 pattern at 11.3 Gbps, LOSRNG = 1
K28.5 pattern at 11.3 Gbps, LOSRNG = 1
Versus temperature at 11.3 Gbps
Versus supply voltage VCC at 11.3 Gbps
Versus data rate
K28.5 pattern at 11.3 Gbps
2
2.5
2.5
2000
32
20
15
35
35
80
1.5
1
1.5
4
10
10
6.5
80
80
BIAS (Reg7 bit 0) set to 1
V
IN
= 15 mV
p-p
, K28.5 pattern
V
IN
= 30 mV
p-p
, K28.5 pattern
V
IN
= 2000 mV
p-p
, K28.5 pattern
V
IN
= 30 mV
p-p
V
IN
> 30 mV
p-p
, DIS = 0, AMP[0..2] = 000
V
IN
> 30 mV
p-p
, DIS = 0, AMP[0..2] = 111
DIS = 1
1
30
30
40
40
7
With 330 pF COC capacitor
PRBS31 pattern at 11.3 Gbps, BER < 10
V
OD-min
≥
0.95 * V
OD
(output limited)
0.01 GHz < f < 5 GHz
5 GHz < f < 12.1 GHz
0.01 GHz < f < 5 GHz
5 GHz < f < 12.1 GHz
0.01 GHz < f < 12.1 GHz
0.01 GHz < f < 5 GHz
5 GHz < f < 12.1 GHz
26
2000
3
3
6
1
380
820
5
8
10
15
ps
rms
mV
p-p
mV
rms
dB
ps
ps
mV
rms
mV
p-p
mV
p-p
dB
dB
dB
dB
µs
µs
µs
µs
ns
ps
p-p
–12
TEST CONDITIONS
VALUE
MIN
7.5
TYP
9.5
10
6
20
–15
–8
–15
–8
–15
–13
–9
33
45
9
40
MAX
UNIT
GHz
kHz
mV
p-p
dB
dB
dB
dB
dB
mV
p-p
Copyright © 2013, Texas Instruments Incorporated
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ONET1151P
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