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OR2C15A4M84-D

fpga - 现场可编程门阵列 1600 lut 298 I/O

器件类别:可编程逻辑器件    可编程逻辑   

厂商名称:Lattice(莱迪斯)

厂商官网:http://www.latticesemi.com

下载文档
器件参数
参数名称
属性值
是否Rohs认证
不符合
零件包装代码
LCC
包装说明
PLASTIC, LCC-84
针数
84
Reach Compliance Code
unknown
ECCN代码
EAR99
其他特性
MAXIMUM USABLE GATES 44200
CLB-Max的组合延迟
2.2 ns
JESD-30 代码
S-PQCC-J84
JESD-609代码
e0
长度
29.083 mm
湿度敏感等级
3
可配置逻辑块数量
400
等效关口数量
19200
输入次数
64
逻辑单元数量
1600
输出次数
64
端子数量
84
最高工作温度
70 °C
最低工作温度
组织
400 CLBS, 19200 GATES
封装主体材料
PLASTIC/EPOXY
封装代码
QCCJ
封装等效代码
LDCC84,1.2SQ
封装形状
SQUARE
封装形式
CHIP CARRIER
峰值回流温度(摄氏度)
225
电源
5 V
可编程逻辑类型
FIELD PROGRAMMABLE GATE ARRAY
认证状态
Not Qualified
座面最大高度
5.08 mm
最大供电电压
5.25 V
最小供电电压
4.75 V
标称供电电压
5 V
表面贴装
YES
技术
CMOS
温度等级
COMMERCIAL
端子面层
Tin/Lead (Sn85Pb15)
端子形式
J BEND
端子节距
1.27 mm
端子位置
QUAD
处于峰值回流温度下的最长时间
30
宽度
29.083 mm
Base Number Matches
1
文档预览
ORCA™ Series 2 Device Datasheet
June 2010
Select Devices Discontinued!
Product Change Notifications (PCNs) have been issued to discontinue select devices in
this data sheet.
The original datasheet pages have not been modified and do not reflect those changes.
Please refer to the table below for reference PCN and current product status.
Product Line
Ordering Part Number
OR2C04A4T100-DB
OR2C04A3T100I-DB
OR2C04A4T144-DB
OR2C04A3T144I-DB
OR2C04A4J160-DB
OR2C04A4S208-DB
OR2C06A4T100-DB
OR2C06A4T144-DB
OR2C06A3T144I-DB
OR2C06A4J160-DB
OR2C06A3J160I-DB
OR2C06A4S208-DB
OR2C06A3S208I-DB
OR2C06A3S240I-DB
OR2C06A4BA256-DB
OR2C06A3BA256I-DB
OR2C08A3J160I-DB
OR2C08A4S208-DB
OR2C08A3S208I-DB
OR2C08A3S240I-DB
OR2C08A3M84I-D
OR2C10A4J160-DB
OR2C10A3J160I-DB
OR2C10A4S208-DB
OR2C10A3BA256I-DB
OR2C10A4BA352-DB
OR2C10A3BA352I-DB
OR2C12A3S208-DB
OR2C12A4S208-DB
OR2C12A3S208I-DB
OR2C12A3S240-DB
OR2C12A4S240-DB
OR2C12A3S240I-DB
Product Status
Reference PCN
OR2C04A
Discontinued
PCN#02-06
OR2C06A
Discontinued
PCN#02-06
OR2C08A
Discontinued
PCN#02-06
OR2C10A
Discontinued
PCN#02-06
OR2C12A
Discontinued
PCN#02-06
5555 N.E. Moore Ct.
Hillsboro, Oregon 97124-6421 Phone (503) 268-8000
Internet: http://www.latticesemi.com
FAX (503) 268-8347
Product Line
OR2C12A
(Cont’d)
OR2C15A
OR2C26A
OR2C40A
OR2T04A
OR2T08A
Ordering Part Number
OR2C12A4BA256-DB
OR2C12A3BA256I-DB
OR2C12A4S304-DB
OR2C12A3S304I-DB
OR2C12A4BA352-DB
OR2C12A3BA352I-DB
OR2C12A4M84-D
OR2C15A4S208-DB
OR2C15A3S208I-DB
OR2C15A3PS208I-DB
OR2C15A4S240-DB
OR2C15A3S240I-DB
OR2C15A4PS240-DB
OR2C15A3PS240I-DB
OR2C15A4BA256-DB
OR2C15A3BA256I-DB
OR2C15A4S304-DB
OR2C15A4BA352-DB
OR2C15A3BA352I-DB
OR2C15A3M84I-D
OR2C26A4PS208-DB
OR2C26A3PS208I-DB
OR2C26A4PS208I-DB
OR2C26A4PS240-DB
OR2C26A3PS240I-DB
OR2C26A4PS304-DB
OR2C26A3PS304I-DB
OR2C40A4PS208-DB
OR2C40A3PS208I-DB
OR2C40A4PS208I-DB
OR2C40A4PS240-DB
OR2C40A4PS304-DB
OR2C40A3PS304I-DB
OR2T04A4T100I-DB
OR2T04A4T144-DB
OR2T04A4S208I-DB
OR2T08A5J160-DB
OR2T08A4J160I-DB
OR2T08A5S208-DB
OR2T08A4S208-DB
OR2T08A4S208I-DB
OR2T08A4S240I-DB
OR2T08A5BA256-DB
OR2T08A4BA256-DB
OR2T08A4BA256I-DB
Product Status
Reference PCN
Discontinued
PCN#02-06
Discontinued
PCN#02-06
Discontinued
PCN#02-06
Discontinued
PCN#02-06
Discontinued
PCN#02-06
Discontinued
PCN#02-06
5555 N.E. Moore Ct.
Hillsboro, Oregon 97124-6421 Phone (503) 268-8000
Internet: http://www.latticesemi.com
FAX (503) 268-8347
Product Line
OR2T10A
OR2T15A
OR2T15B
OR2T26A
OR2T40A
OR2T40B
Ordering Part Number
OR2T10A4J160I-DB
OR2T10A4S208-DB
OR2T10A4S208I-DB
OR2T10A5S240-DB
OR2T10A4S240-DB
OR2T10A4BA256-DB
OR2T15A7S208-DB
OR2T15A6S208-DB
OR2T15A6S208I-DB
OR2T15A7S240-DB
OR2T15A6S240-DB
OR2T15A6S240I-DB
OR2T15A7BA256-DB
OR2T15A6BA256-DB
OR2T15A7BA352-DB
OR2T15A6M84-D
OR2T15B8S208-DB
OR2T15B7S208-DB
OR2T15B7S208I-DB
OR2T15B7S240I-DB
OR2T15B8BA256-DB
OR2T15B7BA256-DB
OR2T15B7BA352-DB
OR2T15B7BA352I-DB
OR2T26A7S208-DB
OR2T26A6S208-DB
OR2T26A6S208I-DB
OR2T26A7PS240-DB
OR2T26A6PS240-DB
OR2T26A6PS240I-DB
OR2T26A6BA352I-DB
OR2T26A6BC432-DB
OR2T26A6BC432I-DB
OR2T40A7PS208-DB
OR2T40A6PS208-DB
OR2T40A6PS208I-DB
OR2T40A7PS240-DB
OR2T40A6PS240-DB
OR2T40A6PS240I-DB
OR2T40A7BA352-DB
OR2T40A6BA352I-DB
OR2T40B7PS208I-DB
OR2T40B8BA352-DB
OR2T40B7BA352-DB
OR2T40B7BA352I-DB
OR2T40B8BC432-DB
OR2T40B7BC432-DB
OR2T40B7BC432I-DB
Product Status
Reference PCN
Discontinued
PCN#02-06
Discontinued
Active / Orderable
Discontinued
Discontinued
Active / Orderable
Discontinued
Discontinued
PCN#09-10
PCN#12A-09
PCN#09-10
PCN#02-06
PCN#09-10
Discontinued
PCN#02-06
Discontinued
Active / Orderable
Discontinued
PCN#09-10
PCN#06-07
Discontinued
PCN#02-06
Discontinued
PCN#06-07
Discontinued
PCN#02-06
Discontinued
PCN#02-06
5555 N.E. Moore Ct.
Hillsboro, Oregon 97124-6421 Phone (503) 268-8000
Internet: http://www.latticesemi.com
FAX (503) 268-8347
5555 N.E. Moore Ct.
Hillsboro, Oregon 97124-6421 Phone (503) 268-8000
Internet: http://www.latticesemi.com
FAX (503) 268-8347
Data Sheet
November 2006
SE
LE
D
IS C
C T
O D
N E
TI VI
N C
U E
ED S
Features
ORCA
®
Series 2
Field-Programmable Gate Arrays
Innovative, abundant, and hierarchical nibble-
oriented routing resources that allow automatic use of
internal gates for all device densities without sacrificing
performance
Upward bit stream compatible with the
ORCA
ATT2Cxx/
ATT2Txx series of devices
Pinout-compatible with new
ORCA
Series 3 FPGAs
TTL or CMOS input levels programmable per pin for the
OR2CxxA (5 V) devices
Individually programmable drive capability:
12 mA sink/6 mA source or 6 mA sink/3 mA source
Built-in boundary scan (
IEEE
*1149.1 JTAG) and
3-state all I/O pins, (TS_ALL) testability functions
Multiple configuration options, including simple, low pin-
count serial ROMs, and peripheral or JTAG modes for in-
system programming (ISP)
Full PCI bus compliance for all devices
Supported by industry-standard CAE tools for design
entry, synthesis, and simulation with ispLEVER Develop-
ment System support (for back-end implementation)
New, added features (OR2TxxB) have:
— More I/O per package than the OR2TxxA family
— No dedicated 5 V supply (V
DD
5)
— Faster configuration speed (40 MHz)
— Pin selectable I/O clamping diodes provide 5V or 3.3V
PCI compliance and 5V tolerance
— Full PCI bus compliance in both 5V and 3.3V PCI sys-
tems
High-performance, cost-effective, low-power
0.35 µm CMOS technology (OR2CxxA), 0.3 µm CMOS
technology (OR2TxxA), and 0.25 µm CMOS technology
(OR2TxxB), (four-input look-up table (LUT) delay less
than 1.0 ns with -8 speed grade)
High density (up to 43,200 usable, logic-only gates; or
99,400 gates including RAM)
Up to 480 user I/Os (OR2TxxA and OR2TxxB I/Os are
5 V tolerant to allow interconnection to both 3.3 V and
5 V devices, selectable on a per-pin basis)
Four 16-bit look-up tables and four latches/flip-flops per
PFU, nibble-oriented for implementing 4-, 8-, 16-, and/or
32-bit (or wider) bus structures
Eight 3-state buffers per PFU for on-chip bus structures
Fast, on-chip user SRAM has features to simplify RAM
design and increase RAM speed:
— Asynchronous single port: 64 bits/PFU
— Synchronous single port: 64 bits/PFU
— Synchronous dual port: 32 bits/PFU
Improved ability to combine PFUs to create larger RAM
structures using write-port enable and 3-state buffers
Fast, dense multipliers can be created with the multiplier
mode (4 x 1 multiplier/PFU):
— 8 x 8 multiplier requires only 16 PFUs
— 30% increase in speed
Flip-flop/latch options to allow programmable priority of
synchronous set/reset vs. clock enable
Enhanced cascadable nibble-wide data path
capabilities for adders, subtractors, counters, multipliers,
and comparators including internal fast-carry operation
*
IEEE
is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
Table 1.
ORCA
Series 2 FPGAs
Device
Usable
Gates*
# LUTs
400
576
784
1024
1296
1600
2304
3600
Registers
400
576
724
1024
1296
1600
2304
3600
Max User
RAM Bits
6,400
9,216
12,544
16,384
20,736
25,600
36,864
57,600
User
I/Os
160
192
224
256
288
320
384
480
Array Size
10 x 10
12 x 12
14 x 14
16 x 16
18 x 18
20 x 20
24 x 24
30 x 30
OR2C04A/OR2T04A
OR2C06A
OR2C08A/OR2T08A
OR2C10A/OR2T10A
OR2C12A
OR2C15A/OR2T15A/OR2T15B
OR2C26A/OR2T26A
OR2C40A/OR2T40A/OR2T40B
4,800—11,000
6,900—15,900
9,400—21,600
12,300—28,300
15,600—35,800
19,200—44,200
27,600—63,600
43,200—99,400
* The first number in the usable gates column assumes 48 gates per PFU (12 gates per four-input LUT/FF pair) for logic-only designs. The
second number assumes 30% of a design is RAM. PFUs used as RAM are counted at four gates per bit, with each PFU capable of
implementing a 16 x 4 RAM (or 256 gates) per PFU.
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