Data Sheet
January 2002
ORCA
®
Series 3C and 3T
Field-Programmable Gate Arrays
Features
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High-performance, cost-effective, 0.35 µm (OR3C) and
0.3 µm (OR3T) 4-level metal technology, (4- or 5-input
look-up table delay of 1.1 ns with -7 speed grade in
0.3 µm).
Same basic architecture as lower-voltage, advanced
process technology Series 3 architectures. (See
ORCA
Series 3L FPGA documentation.)
Up to 186,000 usable gates.
Up to 452 user I/Os. (OR3Txxx I/Os are 5 V tolerant to
allow interconnection to both 3.3 V and 5 V devices,
selectable on a per-pin basis.)
Pin selectable I/O clamping diodes provide 5 V or 3.3 V
PCI compliance and 5 V tolerance on OR3Txxx devices.
Twin-quad programmable function unit (PFU) architec-
ture with eight 16-bit look-up tables (LUTs) per PFU,
organized in two nibbles for use in nibble- or byte-wide
functions. Allows for mixed arithmetic and logic functions
in a single PFU.
Nine user registers per PFU, one following each LUT,
plus one extra. All have programmable clock enable and
local set/reset, plus a global set/reset that can be dis-
abled per PFU.
Flexible input structure (FINS) of the PFUs provides a
routability enhancement for LUTs with shared inputs and
the logic flexibility of LUTs with independent inputs.
Fast-carry logic and routing to adjacent PFUs for nibble-,
byte-wide, or longer arithmetic functions, with the option
to register the PFU carry-out.
Softwired LUTs (SWL) allow fast cascading of up to
three levels of LUT logic in a single PFU for up to 40%
speed improvement.
Supplemental logic and interconnect cell (SLIC) pro-
vides 3-statable buffers, up to 10-bit decoder, and
PAL*-
like AND-OR with optional INVERT in each programma-
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ble logic cell (PLC), with over 50% speed improvement
typical.
Abundant hierarchical routing resources based on rout-
ing two data nibbles and two control lines per set provide
for faster place and route implementations and less rout-
ing delay.
TTL or CMOS input levels programmable per pin for the
OR3Cxx (5.0 V) devices.
Individually programmable drive capability:
12 mA sink/6 mA source or 6 mA sink/3 mA source.
Built-in boundary scan (
IEEE
†
1149.1 JTAG) and
TS_ALL testability function to 3-state all I/O pins.
Enhanced system clock routing for low skew, high-speed
clocks originating on-chip or at any I/O.
Up to four ExpressCLK inputs allow extremely fast clock-
ing of signals on- and off-chip plus access to internal
general clock routing.
StopCLK feature to glitchlessly stop/start ExpressCLKs
independently by user command.
Programmable I/O (PIO) has:
— Fast-capture input latch and input flip-flop (FF) latch
for reduced input setup time and zero hold time.
— Capability to (de)multiplex I/O signals.
— Fast access to SLIC for decodes and
PAL
-like
functions.
— Output FF and two-signal function generator to
reduce CLK to output propagation delay.
— Fast open-drain dive capability
— Capability to register 3-state enable signal.
Baseline FPGA family used in Series 3+ FPSCs (field
programmable system chips) which combine FPGA logic
and standard cell logic on one device.
■
*
PAL
is a trademark of Advanced Micro Devices, Inc.
†
IEEE
is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
Table 1.
ORCA
Series 3 (3C and 3T) FPGAs
Device
OR3T20
OR3T30
OR3C/3T55
OR3C/3T80
OR3T125
System
Gates
‡
36K
48K
80K
116K
186K
LUTs
1152
1568
2592
3872
6272
Registers
1872
2436
3780
5412
8400
Max User RAM
18K
25K
42K
62K
100K
User I/Os
196
228
292
356
452
Array Size
12 x 12
14 x 14
18 x 18
22 x 22
28 x 28
Process
Technology
0.3 µm/4 LM
0.3 µm/4 LM
0.3 µm/4 LM
0.3 µm/4 LM
0.3 µm/4 LM
‡ The system gate counts range from a logic-only gate count to a gate count assuming 30% of the PFUs/SLICs being used as RAMs.
The logic-only gate count includes each PFU/SLIC (counted as 108 gates per PFU/SLIC), including 12 gates per LUT/FF pair (eight per
PFU), and 12 gates per SLIC/FF pair (one per PFU). Each of the four PIOs per PIC is counted as 16 gates (two FFs, fast-capture latch,
output logic, CLK drivers, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing
a 32 x 4 RAM (or 512 gates) per PFU.
ispORCA
Series 3C and 3T FPGAs
Data Sheet
January 2002
Table of Contents
Contents
Page
Contents
Page
Features ......................................................................1
System-Level Features................................................6
Description...................................................................7
FPGA Overview ........................................................7
PLC Logic ..................................................................7
PIC Logic ...................................................................8
System Features .......................................................8
Routing ......................................................................8
Configuration .............................................................8
ORCA
Foundry Development System ......................9
Architecture .................................................................9
Programmable Logic Cells ........................................11
Programmable Function Unit ..................................11
Look-Up Table Operating Modes ............................13
Supplemental Logic and Interconnect Cell (SLIC) ..21
PLC Latches/Flip-Flops ...........................................25
PLC Routing Resources ..........................................27
PLC Architectural Description .................................34
Programmable Input/Output Cells .............................36
5 V Tolerant I/O .......................................................37
PCI Compliant I/O ...................................................37
Inputs ......................................................................38
Outputs ....................................................................41
PIC Routing Resources ...........................................44
PIC Architectural Description ..................................45
High-Level Routing Resources..................................47
Interquad Routing ....................................................47
Programmable Corner Cell Routing ........................48
PIC Interquad (MID) Routing ...................................49
Clock Distribution Network ........................................50
PFU Clock Sources .................................................50
Clock Distribution in the PLC Array .........................51
Clock Sources to the PLC Array .............................52
Clocks in the PICs ...................................................52
ExpressCLK Inputs .................................................53
Selecting Clock Input Pins ......................................53
Special Function Blocks ............................................54
Single Function Blocks ............................................54
Boundary Scan ........................................................57
Microprocessor Interface (MPI) .................................64
PowerPC
System ....................................................65
i960
System ............................................................66
MPI Interface to FPGA ............................................67
MPI Setup and Control ............................................68
Programmable Clock Manager (PCM) ......................72
PCM Registers ........................................................73
Delay-Locked Loop (DLL) Mode .............................75
Phase-Locked Loop (PLL) Mode ............................76
PCM/FPGA Internal Interface .................................79
PCM Operation .......................................................79
PCM Detailed Programming ...................................80
PCM Applications ....................................................83
2
PCM Cautions ........................................................ 84
FPGA States of Operation........................................ 85
Initialization ............................................................. 85
Configuration .......................................................... 86
Start-Up .................................................................. 87
Reconfiguration ...................................................... 88
Partial Reconfiguration ........................................... 88
Other Configuration Options ................................... 88
Configuration Data Format ...................................... 89
Using
ORCA
Foundry to Generate
Configuration RAM Data ....................................... 89
Configuration Data Frame ...................................... 89
Bit Stream Error Checking ...................................... 91
FPGA Configuration Modes...................................... 92
Master Parallel Mode ............................................. 92
Master Serial Mode ................................................ 93
Asynchronous Peripheral Mode ............................. 94
Microprocessor Interface (MPI) Mode .................... 94
Slave Serial Mode .................................................. 97
Slave Parallel Mode ............................................... 97
Daisy-Chaining ....................................................... 98
Daisy-Chaining with Boundary Scan ...................... 99
Absolute Maximum Ratings.................................... 100
Recommended Operating Conditions .................. 100
Electrical Characteristics ........................................ 101
Timing Characteristics ............................................ 103
Description ........................................................... 103
PFU Timing ......................................................... 104
PLC Timing ........................................................... 111
SLIC Timing .......................................................... 111
PIO Timing ........................................................... 112
Special Function Blocks Timing ........................... 115
Clock Timing ......................................................... 123
Configuration Timing ............................................ 133
Readback Timing ................................................. 142
Input/Output Buffer Measurement Conditions ........ 143
Output Buffer Characteristics ................................. 144
OR3Cxx ................................................................ 144
OR3Txxx .............................................................. 145
Estimating Power Dissipation ................................. 146
OR3Cxx ................................................................ 146
OR3Txxx (Preliminary Information) ...................... 147
Pin Information ....................................................... 149
Pin Descriptions ................................................... 149
Package Compatibility .......................................... 153
Compatibility with OR2C/TxxA Series .................. 154
Package Thermal Characteristics........................... 194
Θ
JA ....................................................................... 194
ψ
JC ...................................................................... 194
Θ
JC ...................................................................... 194
Θ
JB ...................................................................... 194
FPGA Maximum Junction Temperature ............... 195
Lattice Semiconductor
Data Sheet
January 2002
ORCA
Series 3C and 3T FPGAs
Table of Contents
Contents
Page
Contents
Page
Package Coplanarity ...............................................196
Package Parasitics ..................................................196
Package Outline Diagrams......................................197
Terms and Definitions ...........................................197
208-Pin SQFP .......................................................198
208-Pin SQFP2 .....................................................199
240-Pin SQFP .......................................................200
240-Pin SQFP2 .....................................................201
256-Pin PBGA .......................................................202
352-Pin PBGA .......................................................203
432-Pin EBGA .......................................................204
600-Pin EBGA .......................................................205
Ordering Information................................................206
Index........................................................................207
Tables
Table 1.
ORCA
Series 3 (3C and 3T) FPGAs ............ 2
Table 2.
ORCA
Series 3 System Performance .......... 6
Table 3. Look-Up Table Operating Modes ............... 13
Table 4. Control Input Functionality .......................... 14
Table 5. Ripple Mode Equality Comparator
Functions and Outputs ............................................ 18
Table 6. SLIC Modes ................................................ 21
Table 7. Configuration RAM Controlled
Latch/Flip-Flop Operation ........................................ 25
Table 8. Inter-PLC Routing Resources ..................... 31
Table 9. PIO Options ................................................ 37
Table 10. PIO Logic Options .................................... 43
Table 11. PIO Register Control Signals .................... 43
Table 12. Readback Options .................................... 54
Table 13. Boundary-Scan Instructions ..................... 58
Table 14. Boundary-Scan ID Code ........................... 59
Table 15. TAP Controller Input/Outputs ................... 61
Table 16.
PowerPC
/MPI Configuration ..................... 65
Table 17.
i960
/MPI Configuration ............................. 66
Table 18. MPI Internal Interface Signals .................. 67
Table 19. MPI Setup and Control Registers ............. 68
Table 20. MPI Setup and Control Registers
Description ............................................................... 68
Table 21. MPI Control Register 2 ............................. 69
Table 22. Status Register ......................................... 70
Table 23. Device ID Code ........................................ 71
Table 24. Series 3 Family and Device ID Values ..... 71
Table 25.
ORCA
Series 3 Device ID Descriptions .... 71
Table 26. PCM Registers ......................................... 73
Table 27. DLL Mode Delay/1x Duty Cycle
Programming Values ............................................... 75
Table 28. DLL Mode Delay/2x Duty Cycle
Programming Values ............................................... 76
Table 29. PCM Oscillator Frequency Range 3Txxx . 78
Table 30. PCM Oscillator Frequency Range 3Cxx ... 78
Table 31. PCM Control Registers ............................. 80
Lattice Semiconductor
Table 32. Configuration Frame Format and
Contents .................................................................. 90
Table 33. Configuration Frame Size ......................... 91
Table 34. Configuration Modes ................................ 92
Table 35. Absolute Maximum Ratings ....................100
Table 36. Recommended Operating Conditions ....100
Table 37. Electrical Characteristics ........................101
Table 38. Derating for Commercial Devices
(OR3Cxx) ..............................................................103
Table 39. Derating for Industrial Devices (OR3Cxx) ....
103
Table 40. Derating for Commercial/Industrial
Devices (OR3Txxx) ...............................................103
Table 41. Combinatorial PFU Timing
Characteristics .......................................................104
Table 42. Sequential PFU Timing Characteristics ..106
Table 43. Ripple Mode PFU Timing
Characteristics .......................................................107
Table 44. Synchronous Memory Write
Characteristics .......................................................109
Table 45. Synchronous Memory Read
Characteristics .......................................................110
Table 46. PFU Output MUX and Direct Routing
Timing Characteristics ...........................................111
Table 47. Supplemental Logic and Interconnect
Cell (SLIC) Timing Characteristics ........................111
Table 48. Programmable I/O (PIO) Timing
Characteristics .......................................................112
Table 49. Microprocessor Interface (MPI) Timing
Characteristics .......................................................115
Table 50. Programmable Clock Manager (PCM)
Timing Characteristics (Preliminary Information) ..121
Table 51. Boundary-Scan Timing Characteristics ..122
Table 52. ExpressCLK (ECLK) and Fast Clock
(FCLK) Timing Characteristics ..............................123
Table 53. General-Purpose Clock Timing
Characteristics (Internally Generated Clock) .........124
Table 54. OR3Cxx ExpressCLK to Output Delay
(Pin-to-Pin) ............................................................125
Table 55. OR3Cxx Fast Clock (FCLK) to Output
Delay (Pin-to-Pin) ..................................................126
Table 56. OR3Cxx General System Clock (SCLK)
to Output Delay (Pin-to-Pin) ..................................127
Table 57. OR3C/Txxx Input to ExpressCLK (ECLK)
Fast-Capture Setup/Hold Time (Pin-to-Pin) ..........128
Table 58. OR3C/Txxx Input to Fast Clock
Setup/Hold Time (Pin-to-Pin) ................................130
Table 59. OR3C/Txxx Input to General System
Clock (SCLK) Setup/Hold Time (Pin-to-Pin) ..........132
Table 60. General Configuration Mode Timing
Characteristics .......................................................133
3
ispORCA
Series 3C and 3T FPGAs
Data Sheet
January 2002
Table of Contents
Contents
Page
Contents
Page
Table 61. Master Serial Configuration Mode Timing
Characteristics ...................................................... 136
Table 62. Master Parallel Configuration Mode Timing
Characteristics ...................................................... 137
Table 63. Asynchronous Peripheral Configuration Mode
Timing Characteristics ........................................... 138
Table 64. Slave Serial Configuration Mode Timing
Characteristics ...................................................... 139
Table 65. Slave Parallel Configuration Mode
Timing Characteristics ........................................... 140
Table 66. Readback Timing Characteristics ........... 142
Table 67. Pin Descriptions ...................................... 149
Table 68.
ORCA
I/Os Summary ............................. 153
Table 69. Series 3 ExpressCLK Pins ..................... 154
Table 70. OR3T20, OR3T30, OR3C/T55,
OR3C/T80, and OR3T125 208-Pin
SQFP/SQFP2 Pinout ............................................ 155
Table 71. OR3T20, OR3T30, OR3C/T55,
OR3C/T80, and OR3T125 240-Pin
SQFP/SQFP2 Pinout ............................................ 161
Table 72. OR3T20, OR3T30, and OR3C/T55
256-Pin PBGA Pinout ............................................ 168
Table 73. OR3T20, OR3T30, OR3C/T55,
OR3C/T80, and OR3T125 352-Pin PBGA Pinout . 172
Table 74. OR3C/T80 and OR3T125 432-Pin
EBGA Pinout ......................................................... 182
Table 75. OR3T125 600-Pin EBGA Pinout ............ 187
Table 76. Plastic Package Thermal
Characteristics for the
ORCA
Series ..................... 195
Table 77. Package Coplanarity .............................. 196
Table 78. Package Parasitics ................................. 196
Table 79. Voltage Options ...................................... 206
Table 80. Temperature Options ............................. 206
Table 81. Package Options .................................... 206
Table 82.
ORCA
Series 3 Package Matrix ............. 206
Table 83. Speed Grade Options ............................. 206
Figures
Figure 1. OR3C/T55 Array ........................................ 10
Figure 2. PFU Ports .................................................. 11
Figure 3. Simplified PFU Diagram ............................ 12
Figure 4. Simplified F4 and F5 Logic Modes ............ 14
Figure 5. Softwired LUT Topology Examples ........... 15
Figure 6. Ripple Mode .............................................. 16
Figure 7. Counter Submode ..................................... 17
Figure 8. Multiplier Submode .................................... 18
Figure 9. Memory Mode ........................................... 19
Figure 10. Memory Mode Expansion Example—
128 x 8 RAM ........................................................... 20
Figure 11. SLIC All Modes Diagram ......................... 22
Figure 12. Buffer Mode ............................................. 22
4
Figure 13. Buffer-Buffer-Decoder Mode ................... 23
Figure 14. Buffer-Decoder-Buffer Mode ................... 23
Figure 15. Buffer-Decoder-Decoder Mode ............... 24
Figure 16. Decoder Mode ......................................... 24
Figure 17. Latch/FF Set/Reset Configurations ......... 26
Figure 18. Configurable Interconnect Point .............. 27
Figure 19. Single PLC View of Inter-PLC Route
Segments ................................................................ 28
Figure 20. Multiple PLC View of Inter-PLC Routing . 32
Figure 21. PLC Architecture ..................................... 35
Figure 22. OR3C/Txxx Programmable Input/Output
(PIO) Image from
ORCA
Foundry ........................... 36
Figure 23. Fast-Capture Latch and Timing ............... 39
Figure 24. PIO Input Demultiplexing ......................... 40
Figure 25. Output Multiplexing (OUT1OUT2 Mode) . 42
Figure 26. Output Multiplexing
(OUT2OUTREG Mode) ........................................... 42
Figure 27. PIC Architecture ...................................... 46
Figure 28. Interquad Routing .................................... 47
Figure 29. hIQ Block Detail ....................................... 48
Figure 30. Top (TMID) Routing ................................. 49
Figure 31. PFU Clock Sources ................................. 50
Figure 32.
ORCA
Series 3 System Clock
Distribution Overview .............................................. 51
Figure 33. PIC System Clock Spine Generation ...... 52
Figure 34. ExpressCLK and Fast Clock Distribution 53
Figure 35. Top CLKCNTRL Function Block .............. 56
Figure 36. Printed-Circuit Board with Boundary-
Scan Circuitry .......................................................... 57
Figure 37. Boundary-Scan Interface ......................... 58
Figure 38.
ORCA
Series Boundary-Scan Circuitry
Functional Diagram ................................................. 60
Figure 39. TAP Controller State Transition Diagram 61
Figure 40. Boundary-Scan Cell ................................ 62
Figure 41. Instruction Register Scan Timing
Diagram ................................................................... 63
Figure 42. MPI Block Diagram .................................. 64
Figure 43.
PowerPC/MPI
.......................................... 65
Figure 44.
i960/MPI
.................................................. 66
Figure 45. PCM Block Diagram ................................ 72
Figure 46. PCM Functional Block Diagram .............. 74
Figure 47. ExpressCLK Delay Minimization Using
the PCM .................................................................. 76
Figure 48. Clock Phase Adjustment Using the PCM 83
Figure 49. FPGA States of Operation ....................... 85
Figure 50. Initialization/Configuration/Start-Up
Waveforms .............................................................. 86
Figure 51. Start-Up Waveforms ................................ 88
Figure 52. Serial Configuration Data Format—
Autoincrement Mode ............................................... 90
Lattice Semiconductor
Data Sheet
January 2002
ORCA
Series 3C and 3T FPGAs
Table of Contents
Contents
Page
Contents
Page
Figure 53. Serial Configuration Data Format—
Explicit Mode ........................................................... 90
Figure 54. Master Parallel Configuration Schematic 92
Figure 55. Master Serial Configuration Schematic ... 93
Figure 56. Asynchronous Peripheral Configuration .. 94
Figure 57.
PowerPC
/MPI Configuration Schematic .. 95
Figure 58.
i960
/MPI Configuration Schematic .......... 95
Figure 59. Configuration Through MPI ..................... 95
Figure 60. Readback Through MPI .......................... 96
Figure 61. Slave Serial Configuration Schematic ..... 97
Figure 62. Slave Parallel Configuration Schematic .. 97
Figure 63. Daisy-Chain Configuration Schematic ..... 98
Figure 64. Combinatorial PFU Timing .................... 105
Figure 65. Synchronous Memory Write
Characteristics ...................................................... 109
Figure 66. Synchronous Memory Read Cycle ........ 110
Figure 67. MPI
PowerPC
User Space Read Timing .....
117
Figure 68. MPI
PowerPC
User Space Write Timing .....
117
Figure 69. MPI
PowerPC
Internal Read Timing ..... 118
Figure 70. MPI
PowerPC
Internal Write Timing ...... 118
Figure 71. MPI
i960
User Space Read Timing ....... 119
Figure 72. MPI
i960
User Space Write Timing ....... 119
Figure 73. MPI
i960
Internal Read Timing .............. 120
Figure 74. MPI
i960
Internal Write Timing .............. 120
Figure 75. Boundary-Scan Timing Diagram ........... 122
Figure 76. ExpressCLK to Output Delay ................ 125
Figure 77. Fast Clock to Output Delay ................... 126
Figure 78. System Clock to Output Delay .............. 127
Figure 79. Input to ExpressCLK Setup/Hold Time ..129
Figure 80. Input to Fast Clock Setup/Hold Time .....131
Figure 81. Input to System Clock Setup/Hold Time 132
Figure 82. General Configuration Mode Timing
Diagram .................................................................135
Figure 83. Master Serial Configuration Mode
Timing Diagram .....................................................136
Figure 84. Master Parallel Configuration Mode
Timing Diagram .....................................................137
Figure 85. Asynchronous Peripheral Configuration
Mode Timing Diagram ...........................................138
Figure 86. Slave Serial Configuration Mode
Timing Diagram .....................................................139
Figure 87. Slave Parallel Configuration Mode
Timing Diagram .....................................................140
Figure 88. Readback Timing Diagram ....................142
Figure 89. ac Test Loads ........................................143
Figure 90. Output Buffer Delays .............................143
Figure 91. Input Buffer Delays ................................143
Figure 92. Sinklim (T
J
= 25 °C, V
DD
= 5.0 V) ..........144
Figure 93. Slewlim (T
J
= 25 °C, V
DD
= 5.0 V) .........144
Figure 94. Fast (T
J
°C, V
DD
= 5.0 V) ......................144
Figure 95. Sinklim (T
J
= 125 °C, V
DD
= 4.5 V) ........144
Figure 96. Slewlim (T
J
= 125 °C, V
DD
= 4.5 V) .......144
Figure 97. Fast (T
J
= 125 °C, V
DD
= 4.5 V) ............144
Figure 98. Sinklim (T
J
= 25 °C, V
DD
= 3.3 V) ..........145
Figure 99. Slewlim (T
J
= 25 °C, V
DD
= 3.3 V) .........145
Figure 100. Fast (T
J
= 25 °C, V
DD
= 3.3 V) ............145
Figure 101. Sinklim (T
J
= 125 °C, V
DD
= 3.0 V) ......145
Figure 102. Slewlim (T
J
= 125 °C, V
DD
= 3.0 V) .....145
Lattice Semiconductor
5
