Preliminary Data Sheet
December 2000
ORCA
®
Series 4
Field-Programmable Gate Arrays
Programmable Features
s
High-performance platform design.
— 0.13 µm seven-level metal technology.
— Internal performance of >250 MHz
(four logic levels).
— I/O performance of >416 MHz for all user I/Os.
— Over 1.5 million usable system gates.
— Meets multiple I/O interface standards.
— 1.5 V operation (30% less power than 1.8 V oper-
ation) translates to greater performance.
— Embedded block RAM (EBR) for onboard stor-
age and buffer needs.
— Built-in system components including an internal
system bus, eight PLLs, and microprocessor
interface.
Traditional I/O selections.
— LVTTL and LVCMOS (3.3 V, 2.5 V, and 1.8 V)
I/Os.
— Per pin-selectable I/O clamping diodes provide
3.3 V PCI compliance.
— Individually programmable drive capability.
24 mA sink/12 mA source, 12 mA sink/6 mA
source, or 6 mA sink/3 mA source.
— Two slew rates supported (fast and slew-limited).
— Fast-capture input latch and input flip-flop (FF)/
latch for reduced input setup time and zero hold
time.
— Fast open-drain drive capability.
— Capability to register 3-state enable signal.
— Off-chip clock drive capability.
— Two-input function generator in output path.
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New programmable high-speed I/O.
— Single-ended: GTL, GTL+, PECL, SSTL3/2
(class I & II), HSTL (Class I, III, IV), zero-bus
turn-around (ZBT*), and double data rate (DDR).
— Double-ended: LDVS, bused-LVDS, LVPECL.
— Customer defined: Ability to substitute arbitrary
standard-cell I/O to meet fast moving standards.
New capability to (de)multiplex I/O signals.
— New DDR on both input and output at rates up to
311 MHz (622 MHz effective rate).
— Used to implement emerging
RapidIO
†
back-
plane interface specification.
— New 2x and 4x downlink and uplink capability per
I/O (i.e., 104 MHz internal to 416 MHz I/O).
Enhanced twin-quad programmable function unit
(PFU).
— Eight 16-bit look-up tables (LUTs) per PFU.
— Nine user registers per PFU, one following each
LUT and organized to allow two nibbles to act
independently, plus one extra for arithmetic
carry/borrow operations.
s
s
s
*
ZBT
is a trademark of Integrated Device Technologies Inc.
†
RapidIO
is a trademark of Motorola, Inc.
Table 1.
ORCA
Series 4—Available FPGA Logic
Device
OR4E2
OR4E4
OR4E6
OR4E10
OR4E14
Columns
26
36
46
60
70
Rows
24
36
44
56
66
PFUs
624
1296
2024
3360
4620
User I/O
400
576
720
928
1088
LUTs
4992
10368
16,192
26,880
36,960
EBR
Blocks
8
12
16
20
24
EBR Bits (k)
74
111
148
185
222
Usable
†
Gates (k)
260—470
400—720
530—970
740—1350
930—1700
† The usable gate counts range from a logic-only gate count to a gate count assuming 20% of the PFUs/SLICs being used as RAMs. The
logic-only gate count includes each PFU/SLIC (counted as 108 gates/PFU), including 12 gates per LUT/FF pair (eight per PFU), and
12 gates per SLIC/FF pair (one per PFU). Each of the four PIO groups are counted as 16 gates (three FFs, fast-capture latch, output logic,
CLK, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 32 x 4 RAM (or
512 gates) per PFU. Embedded block RAM (EBR) is counted as four gates per bit plus each block has an additional 25k gates. 7k gates
are used for each PLL and 50k gates for the embedded system bus and microprocessor interface logic. Both the EBR and PLLs are con-
servatively utilized in the gate count calculations.
Note: Devices are not pinout compatible with
ORCA
Series 2/3.
ORCA
Series 4 FPGAs
Preliminary Data Sheet
December 2000
Table of Contents
Contents
Page
Contents
Page
Programmable Features............................................. 1
System Features .........................................................4
Product Description .....................................................6
Architecture Overview .............................................6
Programmable Logic Cells ..........................................7
Programmable Function Unit ...................................8
Look-Up Table Operating Modes ..........................11
Supplemental Logic and Interconnect Cell ............21
PLC Latches/Flip-Flops .........................................25
Embedded Block RAM ..............................................27
EBR Features ........................................................27
Routing Resources ...................................................31
Clock Distribution Network ........................................31
Primary Clock Nets ................................................31
Secondary Clock and Control Nets .......................31
Edge Clock Nets ....................................................31
Programmable Input/Output Cells .............................31
Programmable I/O .................................................31
Inputs .....................................................................34
Special Function Blocks ............................................38
Microprocessor Interface (MPI) .................................48
Embedded System Bus (ESB) ..................................49
Phase-Locked Loops.................................................52
FPGA States of Operation.........................................55
Initialization............................................................56
Configuration .........................................................56
Start-Up .................................................................56
Reconfiguration .....................................................60
Partial Reconfiguration ..........................................60
Other Configuration Options ..................................60
Bit Stream Error Checking .....................................62
FPGA Configuration Modes.......................................62
Master Parallel Mode.............................................63
Master Serial Mode ...............................................64
Asynchronous Peripheral Mode ............................65
Microprocessor Interface Mode .............................66
Slave Serial Mode .................................................70
Slave Parallel Mode...............................................70
Daisy Chaining ......................................................71
Daisy-Chaining with Boundary Scan .....................72
Absolute Maximum Ratings.......................................72
Recommended Operating Conditions .......................73
Electrical Characteristics ...........................................73
Pin Information ..........................................................75
Pin Descriptions.....................................................75
Package Compatibility ...........................................78
Package Thermal Characteristics Summary ...........118
Θ
JA
......................................................................118
ψ
JC
......................................................................118
Θ
JC
......................................................................118
Θ
JB
......................................................................118
Package Thermal Characteristics............................119
2
Package Coplanarity ...............................................119
Package Parasitics ..................................................119
Package Outline Diagrams......................................120
Terms and Definitions..........................................120
Package Outline Drawings ......................................121
352-Pin PBGA .....................................................121
432-Pin EBGA .....................................................122
680-Pin PBGAM ..................................................123
Ordering Information................................................124
Figure
Page
Figure 1. Series 4 Top-Level Diagram ........................7
Figure 2. PFU Ports .....................................................9
Figure 3. Simplified PFU Diagram .............................10
Figure 4. Simplified F4 and F5 Logic Modes .............12
Figure 5. Simplified F6 Logic Modes .........................13
Figure 6. MUX 4 x 1...................................................13
Figure 7. MUX 8 x 1...................................................14
Figure 8. Softwired LUT Topology Examples.............15
Figure 9. Ripple Mode ...............................................16
Figure 10. Counter Submode ....................................17
Figure 11. Multiplier Submode...................................18
Figure 12. Memory Mode ..........................................19
Figure 13. Memory Mode Expansion
Example—128 x 8 RAM ........................................21
Figure 14. SLIC All Modes Diagram ..........................22
Figure 15. Buffer Mode ..............................................23
Figure 16. Buffer-Buffer-Decoder Mode ....................23
Figure 17. Buffer-Decoder-Buffer Mode ....................24
Figure 18. Buffer-Decoder-Decoder Mode ................24
Figure 19. Decoder Mode..........................................25
Figure 20. Latch/FF Set/Reset Configurations ..........26
Figure 21. EBR Read and Write Cycles
with Write Through ................................................29
Figure 22. Series 4 PIO Image from
ORCA
Foundry ......................................................33
Figure 23.
ORCA
High-Speed I/O Banks ..................36
Figure 24. PIO Shift Register.....................................38
Figure 25. Printed-Circuit Board with Boundary-
Scan Circuitry ........................................................39
Figure 26. Boundary-Scan Interface..........................40
Figure 27.
ORCA
Series Boundary-Scan
Circuitry Functional Diagram .................................43
Figure 28. TAP Controller State Transition
Diagram .................................................................44
Figure 29. Boundary-Scan Cell .................................45
Figure 30. Instruction Register Scan Timing
Diagram .................................................................46
Figure 31. PLL_VF External Requirements...............53
Figure 32. PLL Naming Scheme ...............................54
Lucent Technologies Inc.
Preliminary Data Sheet
December 2000
ORCA
Series 4 FPGAs
Table of Contents
(continued)
Contents
Page
Contents
Page
Figure 33. FPGA States of Operation ....................... 55
Figure 34. Initialization/Configuration/Start-Up
Waveforms............................................................. 57
Figure 35. Start-Up Waveforms................................. 59
Figure 36. Serial Configuration Data
Format—Autoincrement Mode .............................. 60
Figure 37. Serial Configuration Data
Format—Explicit Mode .......................................... 60
Figure 38. Master Parallel
Configuration Schematic ....................................... 63
Figure 39. Master Serial Configuration Schematic.... 65
Figure 40. Asynchronous Peripheral Configuration... 66
Figure 41.
PowerPC/MPI
Configuration Schematic... 67
Figure 42. Configuration Through MPI ...................... 68
Figure 43. Readback Through MPI ........................... 69
Figure 44. Slave Serial Configuration Schematic ...... 70
Figure 45. Slave Parallel Configuration Schematic ... 71
Figure 46. Daisy-Chain Configuration Schematic ..... 72
Figure 47. Package Parasitics ................................. 120
Table 17. PIO Logic Options..................................... 36
Table 18. Compatible Mixed I/O Standards .............. 36
Table 19. LVDS I/O Specifications........................... 37
Table 20. LVDS Termination Pin ............................. 37
Table 21. Dedicated Temperature Sensing.............. 39
Table 22. Boundary-Scan Instructions ..................... 40
Table 23. Series 4E Boundary-Scan
Vendor-ID Codes................................................... 41
Table 24. TAP Controller Input/Outputs ................... 43
Table 25. Readback Options .................................... 46
Table 26. MPC 860 to
ORCA
MPI Interconnection .. 48
Table 27. Embedded System Bus/MPI Registers..... 50
Table 28. Interrupt Register Space Assignments ..... 50
Table 29. Status Register Space Assignments ........ 51
Table 30. Command Register Space Assignments .. 51
Table 31. PPLL Specifications.................................. 52
Table 32. DPLL DS-1/E-1 Specifications.................. 53
Table 33. Dedicated Pin Per Package ...................... 53
Table 34. STS-3/STM-1 DPLL Specifications........... 54
Table 35. Phase-Lock Loops Index .......................... 54
Table 36A. Configuration Frame Format
and Contents ......................................................... 61
Table 36B. Configuration Frame Format
and Contents for Embedded Block RAM............... 61
Table 37. Configuration Frame Size ......................... 62
Table 38. Configuration Modes................................. 63
Table 39. Absolute Maximum Ratings ...................... 73
Table 40. Recommended Operating Conditions....... 73
Table 41. Electrical Characteristics .......................... 73
Table 42. Pin Descriptions........................................ 75
Table 43.
ORCA
I/Os Summary ............................... 78
Table 44. 352-Pin PBGA Pinout ............................... 79
Table 45. 432-Pin EBGA .......................................... 89
Table 46. 680-Pin PBGAM Pinout ............................ 99
Table 47.
ORCA
Series 4 FPGAs Plastic
Package Thermal Guidelines .............................. 119
Table 48.
ORCA
Series 4 FPGAs
Package Parasitics .............................................. 119
Table 49. Series 4 Package Matrix
(Speed Grades)................................................... 124
Table 50. Package Options..................................... 124
Table
Page
Table 1.
ORCA
Series 4—Available FPGA Logic ....... 1
Table 2. System Performance .................................... 5
Table 3. Look-Up Table Operating Modes ................ 11
Table 4. Control Input Functionality .......................... 11
Table 5. Ripple Mode Equality Comparator
Functions and Outputs .......................................... 18
Table 6. SLIC Modes ................................................ 22
Table 7. Configuration RAM Controlled Latch/
Flip-Flop Operation................................................ 25
Table 8.
ORCA
Series 4— Available
Embedded Block RAM .......................................... 27
Table 9. RAM Signals ............................................... 28
Table 10. FIFO Signals ............................................ 29
Table 11. Constant Multiplier Signals ....................... 30
Table 12. 8 x 8 Multiplier Signals.............................. 30
Table 13. CAM Signals ............................................. 30
Table 14. Series 4 Programmable I/O Standards ..... 32
Table 15. PIO Options .............................................. 35
Table 16. PIO Register Control Signals .................... 35
Lucent Technologies Inc.
3
ORCA
Series 4 FPGAs
Preliminary Data Sheet
December 2000
s
Programmable Features
(continued)
— New register control in each PFU has two inde-
pendent programmable clocks, clock enables,
local set/reset, and data selects.
— New LUT structure allows flexible combinations of
LUT4, LUT5, new LUT6, 4-to-1 MUX, new
8-to-1 MUX, and ripple mode arithmetic functions
in the same PFU.
— 32 x 4 RAM per PFU, configurable as single- or
dual-port. Create large, fast RAM/ROM blocks
(128 x 8 in only eight PFUs) using the supplemen-
tal logic and interconnect cell (SLIC) decoders as
bank drivers.
— Softwired LUTs (SWL) allow fast cascading of up
to three levels of LUT logic in a single PFU
through fast internal routing which reduces routing
congestion and improves speed.
— Flexible fast access to PFU inputs from routing.
— Fast-carry logic and routing to all four adjacent
PFUs for nibble-, bytewide, or longer arithmetic
functions, with the option to register the PFU
carry-out.
s
Built-in testability.
— Full boundary-scan (IEEE
2
1149.1 and Draft
1149.2 joint test access group (JTAG)).
— Programming and readback through boundary-
scan port compliant to
IEEE
Draft 1532:D1.7.
— TS_ALL testability function to 3-state all I/O pins.
— New temperature-sensing diode used to deter-
mine device junction temperature.
System Features
s
s
PCI local bus compliant.
Improved
PowerPC
3
860 and
PowerPC
II high-speed
(66 MHz) synchronous MPI interface can be used for
configuration, readback, device control, and device
status, as well as for a general-purpose interface to
the FPGA logic, RAMs, and embedded standard-cell
blocks. Glueless interface to synchronous
PowerPC
processors with user-configurable address space
provided.
New embedded
AMBA
4
specification 2.0 AHB sys-
tem bus (ARM
4
processor) facilitates communication
among the microprocessor interface, configuration
logic, EBR, FPGA logic, and embedded standard-cell
blocks. Embedded 32-bit internal system bus plus
4-bit parity interconnects FPGA logic, microproces-
sor interface (MPI), embedded RAM blocks, and
embedded standard-cell blocks with 100 MHz bus
performance. Included are built-in system registers
that act as the control and status center for the
device.
New network phase-locked loops (PLLs) meet ITU-T
G.811 specifications and provide clock conditioning
for DS-1/E-1 and STS-3/STM-1 applications.
Flexible general-purpose programmable PLLs offer
clock multiply (up to 8x), divide (down to 1/8x), phase
shift, delay compensation, and duty cycle adjustment
combined. Improved built-in clock management with
programmable phase-locked loops (PPLLs) provide
optimum clock modification and conditioning for
phase, frequency, and duty cycle from 20 MHz up to
420 MHz. Each PPLL provides two separate clock
outputs.
s
Abundant high-speed buffered and nonbuffered rout-
ing resources provide 2x average speed improve-
ments over previous architectures.
Hierarchical routing optimized for both local and glo-
bal routing with dedicated routing resources. This
results in faster routing times with predictable and
efficient performance.
SLIC provides eight 3-statable buffers, up to 10-bit
decoder, and
PAL
1
-like and-or-invert (AOI) in each
programmable logic cell.
New 200 MHz embedded quad-port RAM blocks, two
read ports, two write ports, and two sets of byte lane
enables. Each embedded RAM block can be config-
ured as:
— One 512 x 18 (quad-port, two read/two write) with
optional built-in arbitration.
— One 256 x 36 (dual-port, one read/one write).
— One 1K x 9 (dual-port, one read/one write).
— Two 512 x 9 (dual-port, one read/one write for
each).
— Two RAMs with arbitrary number of words whose
sum is 512 or less by 18 (dual-port, one read/one
write).
— Supports joining of RAM blocks.
— Two 16 x 8-bit content addressable memory
(CAM) support.
— FIFO 512 x 18, 256 x 36, 1K x 9 or dual 512 x 9.
— Constant multiply (8 x 16 or 16 x 8).
— Dual-variable multiply (8 x 8).
s
s
s
s
s
1. PAL
is a trademark of Advanced Micro Devices, Inc.
2.
IEEE
a is registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
3.
PowerPC
is a registered trademark of International Business
Machines, Corporation.
4.
AMBA
and
ARM
are trademarks of ARM Limited.
4
Lucent Technologies Inc.
Preliminary Data Sheet
December 2000
ORCA
Series 4 FPGAs
System Features
(continued)
s
s
s
Variable-size bused readback of configuration data capability with the built-in MPI and system bus.
Internal, 3-state, bidirectional buses with simple control provided by the SLIC.
Meets universal test and operations PHY interface for ATM (UTOPIA) Levels 1, 2, and 3. Also meets proposed
specifications for UTOPIA Level 4 for 10 Gbits/s interfaces.
New clock routing structures for global and local clocking significantly increases speed and reduces skew
(<200 ps for OR4E4).
New local clock routing structures allow creation of localized clock trees anywhere on the device.
New DDR, QDR, and
ZBT
memory interfaces support the latest high-speed memory interfaces.
New 2x/4x uplink and downlink I/O shift registers capabilities interface high-speed external I/Os to reduced inter-
nal logic speed.
ORCA
Foundry 2000 development system software. Supported by industry-standard CAE tools for design entry,
synthesis, simulation, and timing analysis.
s
s
s
s
s
Table 2. System Performance
Function
16-bit loadable up/down counter
16-bit accumulator
8 x 8 Parallel Multiplier
Multiplier mode, unpipelined
1
ROM mode, unpipelined
2
Multiplier mode, pipelined
3
32 x 16 RAM (synchronous)
Single port, 3-state bus
4
Dual-port
5
128 x 8 RAM (synchronous)
Single port, 3-state bus
4
Dual-port, 3-state bus
5
Address Decode
8-bit internal, LUT-based
8-bit internal, SLIC-based
6
32-bit internal, LUT-based
32-bit internal, SLIC-based
7
36-bit Parity Check (internal)
0.25
0
2
0
2
1.37
0.73
4.68
2.08
4.68
ns
ns
ns
ns
ns
8
8
264
264
MHz
MHz
4
4
264
340
MHz
MHz
11.5
8
15
72
175
197
MHz
MHz
MHz
No. PFUs
2
2
2
282
282
Unit
MHz
MHz
1. Implemented using 8 x 1 multiplier mode (unpipelined), register-to-register, two 8-bit inputs, one 16-bit output.
2. Implemented using two 32 x 4 RAMs and one 12-bit adder, one 8-bit input, one fixed operand, one 16-bit output.
3. Implemented using 8 x 1 multiplier mode (fully pipelined), two 8-bit inputs, one 16-bit output (seven of 15 PFUs
contain only pipelining registers).
4. Implemented using 32 x 4 RAM mode with read data on 3-state buffer to bidirectional read/write bus.
5. Implemented using 32 x 4 dual-port RAM mode.
6. Implemented in one partially occupied SLIC, with decoded output setup to CE in the same PLC.
7. Implemented in five partially occupied SLICs.
Lucent Technologies Inc.
5
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