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P1011NXN2HFB

IC MPU Q OR IQ 800MHZ 689TEBGA

器件类别:嵌入式处理器和控制器    微控制器和处理器   

厂商名称:NXP(恩智浦)

厂商官网:https://www.nxp.com

器件标准:

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器件参数
参数名称
属性值
Brand Name
Freescale
是否无铅
不含铅
是否Rohs认证
符合
厂商名称
NXP(恩智浦)
包装说明
31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, WBTEBGAII-689
Reach Compliance Code
compliant
ECCN代码
3A991.A.2
地址总线宽度
位大小
32
边界扫描
YES
最大时钟频率
100 MHz
外部数据总线宽度
格式
FLOATING POINT
集成缓存
YES
JESD-30 代码
S-PBGA-B689
JESD-609代码
e2
长度
31 mm
低功率模式
YES
湿度敏感等级
3
端子数量
689
最高工作温度
125 °C
最低工作温度
-40 °C
封装主体材料
PLASTIC/EPOXY
封装代码
HBGA
封装形状
SQUARE
封装形式
GRID ARRAY, HEAT SINK/SLUG
峰值回流温度(摄氏度)
260
座面最大高度
2.46 mm
速度
800 MHz
最大供电电压
1.05 V
最小供电电压
0.95 V
标称供电电压
1 V
表面贴装
YES
技术
CMOS
温度等级
AUTOMOTIVE
端子面层
Tin/Silver (Sn/Ag)
端子形式
BALL
端子节距
1 mm
端子位置
BOTTOM
处于峰值回流温度下的最长时间
40
宽度
31 mm
uPs/uCs/外围集成电路类型
MICROPROCESSOR, RISC
文档预览
TM
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, t
he Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony
are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack,
ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a Package, Processor Expert, QorIQ
Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks
of Freescale Semiconductor, Inc. All other product or service names are the property
of their respective owners. © 2011 Freescale Semiconductor, Inc.
Title:
Duplicate edge-triggered interrupt after priority re-arbitration.
Description:
There is an occurrence of duplicate interrupt when an edge-triggered interrupt higher in priority comes closely to any other enabled interrupts. The following
is the sequence of events that leads to the duplicate edge-triggered interrupt::
1. An active interrupt is waiting for acknowledgement
2. An edge-triggered interrupt of higher priority triggers closely to the lower priority interrupt just when it is acknowledged
3. The higher priority edge-triggered interrupt supersedes and fires a new interrupt to the core
4. The core acknowledges the higher priority interrupt without clearing the pending state and finishes the interrupt service routine with EOI
5. A duplicate of the higher priority edge-triggered interrupt is triggered because of the uncleared pending state
Impact:
Enabling any edge-triggered interrupts higher in priority than other enabled interrupts may lead to the duplicate edge-triggered interrupt. This includes
edge-triggered IRQs, global timers and IPI.
Workaround:
Chose one of the following workarounds based on the interrupt type:
• Configure the higher priority interrupts as level-sensitive only
a. In case of IRQs this can be configured in the Vector/Priority Register.
b. It is not an option for global timers or IPI.
• Any enabled edge-triggered interrupts must be no higher in priority than the other enabled interrupts.
Resolution:
No plan to fix
TM
2
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore
and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a
Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc.
All other product or service names are the property of their respective owners. © 2011 Freescale Semiconductor, Inc.
TM
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