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Vishay Sfernice
High Precision Wraparound - Wide Ohmic Value Range
Thin Film Chip Resistors
FEATURES
• Load life stability at ± 70 °C for 2000 h:
0.1 % under Pn/0.05 % under Pd
• Low temperature coefficient down to
5 ppm/°C
(- 55 °C; + 155 °C)
• Very low noise < - 35 dB and voltage coefficient
< 0.01 ppm/V
• Wide resistance range: 10
to 76 M
depending on size
• Tolerances to
± 0.01 %
For low noise and precision applications, superior stability,
low temperature coefficient of resistance, and low voltage
coefficient, Vishay Sfernice’s proven precision thin film
wraparound
resistors
exceed
requirements
of
MIL-PRF-55342G characteristics Y ± 10 ppm/°C (- 55 °C;
+ 155 °C) down to ± 5 ppm/°C (- 55 °C; + 155 °C).
• In lot tracking
5 ppm/°C
• Termination: Thin film technology
• Gold plated or pre-tinned terminations over nickel barrier
• Short circuits (jumpers) r < 50 mR, I < 2 A, see PZR
datasheet (www.vishay.com/doc?53053)
• SMD wraparound terminations
• Withstand moisture resistance test of AEC-Q200
• Compliant to RoHS Directive 2002/95/EC
Notes
*
Pb containing terminations are not RoHS compliant, exemptions
may apply
**
Please see document “Vishay Material Category Policy”:
www.vishay.com/doc?99902
DIMENSIONS
in millimeters (inches)
A
D
D
C
B
E
E
A
CASE SIZE
MAX. TOL.
+ 0.152 (+ 0.006)
MIN. TOL.
- 0.152 (- 0.006)
NOMINAL
0302
0402
0505
0603
0705/0805
1005
1206
1505
2010
0.75 (0.029)
1.00 (0.039)
1.27 (0.005)
1.52 (0.060)
1.91 (0.075)
2.54 (0.100)
3.06 (0.120)
3.81 (0.150)
5.08 (0.200)
B
MAX. TOL.
+ 0.127 (+ 0.005)
MIN. TOL.
- 0.127 (- 0.005)
NOMINAL
0.60 (0.024)
0.60 (0.024)
1.27 (0.050)
0.85 (0.033)
1.27 (0.050)
1.27 (0.050)
1.60 (0.063)
1.32 (0.052)
2.54 (0.100)
0.40 (0.016)
0.48 (0.019)
0.5 (0.02)
± 0.127 (0.005)
0.38 (0.015)
0.13 (0.005)
C
NOMINAL
0.15 (0.006)
0.25 (0.010)
D/E
TOLERANCE
0.08 (0.003)
0.1 (0.004)
Note
• Case size 2512 under development. Please consult Vishay Sfernice.
Revision: 08-Sep-11
1
For technical questions, contact:
sfer@vishay.com
Document Number: 53017
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
P
www.vishay.com
SUGGESTED LAND PATTERN
(to IPC-7351A)
Vishay Sfernice
G
min.
X
max.
Z
max.
DIMENSIONS (in millimeter)
CHIP SIZE
Z
max.
0302
0402
0505
0603
0705/0805
1005
1206
1505
2010
1.30
1.55
1.82
2.37
2.76
3.39
3.91
4.66
5.93
G
min.
0.14
0.15
0.10
0.35
0.74
1.37
1.85
2.44
3.71
X
max.
0.73
0.73
1.40
0.98
1.40
1.40
1.73
1.45
2.67
Note
• Case size 2512 under development. Please consult Vishay Sfernice.
ELECTRICAL SPECIFICATIONS
POWER RATING
mW
Pn
(1)
0302
0402
0505
0603
0705/0805
1005
1206
1505
2010
40
63
125
125
200
250
330
350
1000
Pd
(1)
30
40
50
100
125
125
250
175
500
CASE SIZE
LIMITING ELEMENT VOLTAGE
V
25
50
50
75
150
75
200
75
300
RESISTANCE RANGE
(2)
10
to 750 k
10
to 1.5 M
10
to 4 M
10
to 3.2 M
10
to 10 M
10
to 8.1 M
10
to 35 M
10
to 15 M
10
to 76 M
Notes
• Case size 2512 under development. Please consult Vishay Sfernice.
(1)
Pn = Nominal power - Pd = Derated power intended to improve stability.
(2)
For ohmic range versus tolerance and TCR see detailed table on next page.
Revision: 08-Sep-11
2
For technical questions, contact:
sfer@vishay.com
Document Number: 53017
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
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ELECTRICAL SPECIFICATIONS
Resistance range:
Resistance tolerance:
Power dissipation:
10
to 76 M
0.01 % to 1 %
Pn:
40 mW to 1 W
Pd:
40 mW to 500 mW
Vishay Sfernice
TEMPERATURE COEFFICIENT
TCR
± 5 ppm/°C
(1)
± 5 ppm/°C
(1)
(1)
CODE
C (- 55 °C; + 155 °C)
Z (0 °C; + 70 °C)
Y
E
H
K
FILM
NiCr
NiCr
NiCr
NiCr
NiCr or CrSi
NiCr or CrSi
± 10 ppm/°C
± 25 ppm/°C
± 50 ppm/°C
Temperature coefficient:
Down to 5 ppm - 55 °C; + 155 °C
CLIMATIC SPECIFICATIONS
Operating temp. range:
- 55 °C to + 155 °C
For temperature up to 230 °C, see PHT datasheet
(www.vishay.com/doc?53050)
± 100 ppm/°C
Note
(1)
R > 39
on request for lower values.
POWER DERATING CURVE
Substrate:
Technology:
Film:
Protection:
Terminations:
Alumina
Thin film
Nickel chromium
with mineral
passivation or
CrSi
Silicone
B type:
SnPb over nickel barrier
for solder reflow
N type:
SnAg over nickel barrier
G type:
gold over nickel barrier
for other applications
Rated Power (%)
MECHANICAL SPECIFICATIONS
100
80
60
40
20
0
0
20
40
60 70 80
100
120
140 155
Ambient Temperature in °C
BEST TOLERANCE AND TCR VS. OHMIC VALUE
P2010
P1505
P1206
P1005
10
Ω
100
Ω
250
Ω
P0805
P0603
P0505
P0402
P0302
0.05 %
0.02 %
0.01 %
3M8
720K
1M3
400K
360K
160K
187K
67K
35K
5M
1M
2M
550K
511K
332K
260K
100K
50K
0.05 %
7M5
1M5
3M5
810K
750K
500K
400K
150K
75K
0.1 %
76M
15M
35M
8M1
10M
3M2
4M
1M5
750K
TCR C
TCR Z, Y
TCR E
TCR H, K
Revision: 08-Sep-11
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For technical questions, contact:
sfer@vishay.com
Document Number: 53017
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
P
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POPULAR OPTIONS
For any option it is recommended to consult Vishay Sfernice for availability first.
Option: Enlarged terminations:
For stringent and special power dissipation requirements, the thermal resistance between the resistive layer and the solder joint
can be reduced using enlarged terminations chip resistors which are soldered on large and thick copper pads acting as heatsink
(see application note: 53048 Power Dissipation in High Precision Vishay Sfernice Chip Resistors and Arrays (P Thin Film, PRA
Arrays, CHP Thick Film)
www.vishay.com/doc?53048.
Option to order: 0063 (applies to size 1206/1505/2010).
Vishay Sfernice
DIMENSIONS
(Option 0063) in millimeters
Bottom view for mounting
A
Uncoatted
ceramic
Enlarged
termination
B
F
D
E
A
MAX. TOL.
+ 0.152
MIN. TOL.
- 0.152
NOMINAL
1206
1505
2010
3.06
3.81
5.08
B
MAX. TOL.
+ 0.127
MIN. TOL.
- 0.127
NOMINAL
1.60
1.32
2.54
E
MAX. TOL.
+ 0.13
MIN. TOL.
- 0.13
NOMINAL
0.40
0.48
D
MAX. TOL.
+ 0.13
MIN. TOL.
- 0.13
NOMINAL
1.215
1.59
2.25
0.63
0.50
0.76
NOMINAL
F
CASE SIZE
MIN.
MAX.
Note
• Case size 2512 under development. Please consult Vishay Sfernice.
SUGGESTED LAND PATTERN
(Option 0063)
G
min.
X
max.
Z
max.
CHIP SIZE
1206
1505
2010
DIMENSIONS (IN MILLIMETER)
Z
max.
3.91
4.66
5.93
0.50
G
min.
X
max.
1.73
1.45
2.67
Note
• Case size 2512 under development. Please consult Vishay Sfernice.
Revision: 08-Sep-11
4
For technical questions, contact:
sfer@vishay.com
Document Number: 53017
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
P
www.vishay.com
Option: Marking
Option to order 0013:
Marking of ohmic value and tolerance:
Sizes: 0805 to 1005: 3 digits marking (according to EIA-96)
Sizes: 1206 to 2010: 4 digits marking (same codification than in the ordering procedure)
Tolerance indicated by a color dot.
Option to order 0014:
Marking of ohmic value:
Sizes: 0805 to 1005: 3 digits marking (according to EIA-96)
Sizes: 1206 to 2010: 4 digits marking (same codification than in the ordering procedure)
No standard marking available for smaller sizes.
A price adder will apply to the unit price of the parts for options 0013 and 0014.
Option: AEC-Q200
Moisture resistance
Option to Order 0058:
Specific production process to withstand 85 °C/85 % at Pn/10
Vishay Sfernice
PACKAGING
ESD packaging available: waffle-pack, and plastic tape and
reel (low conductivity). Paper tape available upon request
(ESD only) (for size 0603, 0805, and 1206).
NUMBER OF PIECES PER PACKAGE
TAPE
SIZE MOQ WAFFLE PACK
TAPE AND REEL
WIDTH
2" × 2"
MIN.
MAX.
0302
0402
5000
0505
100
0603
100
8 mm
0805
100
0705
1005
221
4000
1206
140
1505
60
2010
100
2000
8 mm
PACKAGING RULES
Waffle Pack
Can be filled up to maximum quantity indicated in the table
here above, taking into account the minimum order quantity.
When quantity ordered exceeds maximum quantity of a
single waffle pack, the waffle packs are stacked up on the
top of each other and closed by one single cover.
To get “not stacked up” waffle pack in case of ordered
quantity > maximum number of pieces per package:
Please consult Vishay Sfernice for specific ordering
code.
Tape and Reel
Can be filled up to maximum quantity indicated in the table
here above, taking into account the minimum order quantity.
When quantity ordered is between the MOQ and the
maximum reel capacity, only one reel is provided.
When several reels are needed for ordered quantity
within MOQ and maximum reel capacity: Please consult
Vishay Sfernice for specific ordering code.
PERFORMANCE
TESTS
Thermal shock
Short time overload
Low temperature operation
Resistance to solder heat
CONDITIONS
MIL-PRF-55342G
MIL-STD-202 F-Method 107 F
MIL-PRF-55342G
PARA 3.10.4.7.5
MIL-PRF-55342G
PARA 3.9 and 4.7.4
MIL-PRF-55342G
PARA 3.12, 4.7.7, 4.7.1.2
MIL-PRF-55342G
PARA 3.13 and 4.7.8
MIL-STD-202 F-Method 106 E
CECC 56 days/40 °C/93 % RH
AEC-Q200
(2)
85 °C/85 % RH/Pn/10
1000 h
MIL-PRF-55342G
PARA 3.11 and 4.7.6
MIL-PRF-55342G
2000 h Pn at 70 °C
MIL-STD-202 F-Method 108 A
MIL OR CECC
REQUIREMENTS
± 0.05 %
± 0.05 %
± 0.05 %
± 0.05 %
± 0.10 %
± 0.10 %
± 0.5 % + 0.05
± 0.05 %
± 0.5 %
TYPICAL
PERFORMANCES
± 0.02 %
± 0.01 %
± 0.01 %
± 0.03 %
± 0.01 %
± 0.01 %
Max. < 0.3 % + 0.05
± 0.05 %
± 0.10 %
(1)
Moisture resistance
High temperature
Load life
Notes
(1)
0.05 % under Pd
(2)
Option to order
Revision: 08-Sep-11
5
For technical questions, contact:
sfer@vishay.com
Document Number: 53017
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
FPGA/CPLD
