PACE1750AE
SINGLE CHIP, 20MHz to 40MHz, ENHANCED
CMOS 16-BIT PROCESSOR
FEATURES
Implements the MIL-STD-1750A Instruction Set
Architecture
Single Chip PACE Technology
TM
CMOS 16-Bit
Processor with 32 and 48-Bit Floating Point
Arithmetic
Form-Fit-Functionally Compatible with the
P1750A
DAIS Instruction Mix Execution Performance
Including Floating Point Arithmetic
1.8 MIPS at 20 MHz
2.7 MIPS at 30 MHz
3.6 MIPS at 40 MHz
Conventional Integer Processing Mix
Performance
5.0 MIPS at 40 MHz
Power BIF Instructions Allow for High
Throughput Implementations of Transcedental
Functions, Navigational Algorithms and DSP
Functions
– Inner Dot Product Instruction for 3X3, 16 Bit
Registers in 150ns (2 clocks per Multiply/
Accumulate step) with 32 Bits Result
– Multiply/Accumulate Instructions for 32 Bit
Registers is 200ns at 40MHz (8 clocks), with
48 Bit Result
– Parameteric Memory Inner-Dot Products for
Matrix Computations up to 64K
– Fast Polynomial expansion algorithms
– Fast context switching with Instruction to
block move up to 16 new mapping memory
page registers
20, 30, and 40 MHz Operation over the Military
Temperature Range
Extensive Error and Fault Management and
Interrupt Capability
26 User Accessible Registers
Single 5V ± 10% Power Supply
Power Dissipation over Military Temperature
Range
<0.5 watts at 20 & 30 MHz
<1.0 watts at 40 MHz
TTL Signal Level Compatible Inputs and
Outputs
Multiprocessor and Co-processor Capability
Two programmable Timers
Available in:
– 64-Pin Top Brazed DIP
– 68-Pin Pin Grid Array (PGA)
– 68-Lead Quad Pack (Leaded Chip Carrier)
GENERAL DESCRIPTION
The PACE1750AE is a general purpose, single chip, 16-
bit CMOS microprocessor designed for high performance
floating point and integer arithmetic, with extensive real
time environment support. It offers a variety of data types,
including bits, bytes, 16-bit and 32-bit integers, and 32-bit
and 48-bit floating point numbers. It provides 13 addressing
modes, including direct, indirect, indexed, based, based
indexed and immediate long and short, and it can access
2 MWords of segmented memory space (64 KWords
segments).
The PACE1750AE offers a well-rounded instruction set
with 130 instruction types, including a comprehensive
integer, floating point, integer-to-floating point and floating
point-to-integer set, a variety of stack manipulation
instructions, high level language support instructions
such as Compare Between Bounds and Loop Control
Instructions. It also offers some unique instructions such
as vectored l/O, supports executive and user modes, and
provides an escape mechanism which allows user-defined
instructions, using a coprocessor.
The chip includes an array of real time application support
resources, such as 2 programmable timers, a complete
interrupt controller supporting 16 levels of prioritized
internal and external interrupts, and a faults and exceptions
handler controlling internally and externally generated
faults.
The microprocessor achieves very high throughput of 3.6
MIPS for a standard real time integer/floating point
instruction mix at a 40 MHz clock. It executes integer Add
in 0.1 µs, integer Multiply in 0.1 µs, Floating Point Add in
0.45 µs, and Floating Point Multiply in 0.225 µs, for
register operands at a 40 MHz clock speed.
The PACE1750AE uses a single multiplexed 16-bit parallel
bus. Status signals are provided to determine whether
the processor is in the memory or I/O bus cycle, reading
and writing, and whether the bus cycle is for data or
instructions.
Document #
MICRO-2
REV G
Revised October 2005
PACE1750AE
DIFFERENCES BETWEEN THE PACE1750A AND PACE1750AE
The PACE1750AE achieves a 41% boost in performance (in clock cycles) over the PACE1750A. This reduction in clocks
per instruction is because of three architectural enhancements:
1) The inclusion of a 24 x 24 Multiply Accumulate (MAC) array.
2) A reduction in non-bus cycles to 2 clocks (bus cycles remain at 4 clocks to maintain full compatibility with CPU’s
peripheral chips).
3) Branch calculation logic.
The table below shows how the MAC improves all multiply operations — both integer and floating point — by 477% to
760%.
PACE1750AE
Instruction
Integer Add/Sub
Double Precision Integer Add/Sub
Integer Multiply
Double Precision Integer Add/Sub
Floating Add/Sub
Extended Floating Add/Sub
Floating Multiply
Extended Floating Point Multiply
Branch (Taken)
Branch (Not Taken)
Flt’g’ Point Polynomial Step (Mul+Add/Sub)
Ext Flt’g’ Point Polynomial Step (Mul/Sub)
DAIS Mix (MIPS)
Clocks
4
6
4
9
18
34
9
17
8
4
27
51
—
Execution
Time (40 MHz)
100ns
150ns
100ns
225ns
450ns
850ns
225ns
425ns
200ns
100ns
675ns
1275ns
3.56
PACE1750A
Clocks
4
9
23
69
28
51
43
96
12
4
71
147
—
Execution
Gain
Time (40 MHz) #Clocks (%)
100ns
225ns
575ns
1725ns
700ns
1225ns
1075ns
2400ns
300ns
100ns
1775ns
3675ns
2.52
—
50
575
760
55
50
477
564
50
—
263
2400
41/59
PACE1750AE BUILT IN FUNCTIONS
A core set of additional instructions have been included in the PACE1750AE. These instructions utilize the Built ln Function
(BlF) opcode space. The objective of these new opcodes is to enhance the performance of the PACE in critical application
areas such as navigation, DSP, transcendentals and other LINPAK and matrix type instructions. Below is a list of the BlFs
and their execution times (N = the number of elements in the vector being processed).
Instruction
Memory Parametric Dot Product—Single
Memory Parametric Dot Product—Double
3 x 3 Register Dot Product
Double Precision Multiply Accumulate
Polynomial
Clear Accumulator
Store Accumulator (32-Bit)
Store Accumulator (48-Bit)
Load Accumulator (32-Bit)
Load Accumulator Long (48-Bit)
Move MMU Page Block
Load Timer A Reset Register
Load Timer B Reset Register
Mnemonic
VDPS
VDPD
R3DP
MACD
POLY
CLAC
STA
STAL
LAC
LACL
MMPG
LTAR
LTBR
Address
Mode
4F3(RA)
4F1(RA)
4F03
4F02
4F06
4F00
4F08
4F04
4F05
4F07
4F0F
4F0D
4F0E
Number of
Clocks
10 + 8 • N
10+16 • N
6
8
7•N-2
4
7
11
9
9
16+8 • N
4
4
Privileged
Notes
Interruptable
Interruptable
Document #
MICRO-2
REV G
Page 2 of 25
PACE1750AE
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage Range
Input Voltage Range
-0.5V to 7.0V
-0.5V to V
CC
+ 0.5V
Thermal resistance, junction-to-case (Θ
JC
), Note 5:
Θ
Cases X and T
Cases Y and U
Case Z
8°C/W
5°C/W
6°C/W
Storage Temperature Range -65°C to + 150°C
Input Current Range
Voltage Applied to Inputs
Current Applied to Outputs
3
-30mA to +5mA
-0.5V to VCC + 0.5V
150 mA
RECOMMENDED OPERATING
CONDITIONS
Supply Voltage Range
4.5V to 5.5V
Case Operating Temperature -55°C to +125°C
Range
Maximum Power Dissipation
2
1.5W
Operating worst case power dissipation (outputs
open), Note 4:
Device type 05 (20 MHz)
Device type 06 (30 MHz)
Device type 07 (40 MHz)
Lead Temperature Range
(soldering 10 seconds)
0.4W at 20 MHz
0.5W at 30 MHz
0.6W at 40 MHz
300° C
NOTE 1:
Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may
degrade performance and affect reliability.
NOTE 2:
Must withstand the added power dissipation due to short circuit test e.g., I
OS
NOTE 3:
Duration one second or less.
NOTE 4: Device Type Definitions from 5962-87665 SMD:
Device Type 05: 20 MHz
Device Type 06: 30 MHz
Device Type 07: 40 MHz
NOTE 5: Case Definitions from 5962-87665 SMD:
Case X: Dual In-Line
Case T: Dual In-Line with Gull-Wing Leads
Case Y: Leaded Chip Carrier with Gull-Wing Leads
Case U: Leaded Chip Carrier with Unformed Leads
Case Z: Pin Grid Array
Document #
MICRO-2
REV G
Page 3 of 25
PACE1750AE
DC ELECTRICAL SPECIFICATIONS
(Over recommended operating conditions)
Symbol
V
IH
V
IL
V
CD
V
OH
Parameter
Input HIGH Level Voltage
Input LOW Level Voltage
2
Input Clamp Diode Voltage
Output HIGH Level Voltage
2.4
V
CC
– 0.2
V
OL
Output LOW Level Voltage
Input HIGH Level Current,
I
IH1
except IB
0
– IB
15
,
BUS BUSY, BUS LOCK
I
IH2
Input HIGH Level Current,
IB
0
– IB
15
,
BUS BUSY, BUS LOCK
I
IL1
Input LOW Level Current,
except IB
0
– IB
15
,
BUS BUSY, BUS LOCK
Input LOW Level Current,
IB
0
– IB
15
,
BUS BUSY, BUS LOCK
Output Three-State Current
Output Three-State Current
Quiescent Power Supply
Current (CMOS Input
Levels)
Quiescent Power Supply
Current (TTL Input
Levels)
Dynamic Power
I
CCD
Supply Current
20 MHz
30 MHz
40 MHz
I
OS
C
IN
C
OUT
C
I/O
Output Short Circuit Current
3
Input Capacitance
Output Capacitance
Bi-directional Capacitance
–25
10
15
15
–10
µA
V
IN
= GND, V
CC
= 5.5V
50
µA
V
IN
= V
CC
, V
CC
= 5.5V
10
µA
V
IN
= V
CC
, V
CC
= 5.5V
0.5
0.2
Min
2.0
–0.5
Max
V
CC
+ 0.5
0.8
–1.2
Unit
V
V
V
V
V
V
V
V
CC
= 4.5V, I
IN
= –18mA
V
CC
= 4.5V
V
CC
= 4.5V
V
CC
= 4.5V
V
CC
= 4.5V
I
OH
= –8.0mA
I
OH
= –300µA
I
OL
= 8.0mA
I
OL
= 300µA
Conditions
1
I
IL2
I
OZH
I
OZL
I
CCQC
–50
50
–50
20
µA
µA
µA
mA
V
IN
= GND, V
CC
= 5.5V
V
OUT
= 2.4V, V
CC
= 5.5V
V
OUT
= 0.5V, V
CC
= 5.5V
V
IN
< 0.2V or < V
CC
– 0.2V,
f = 0MHz, Outputs Open,
V
CC
= 5.5V
V
IN
< 3.4V, f = 0MHz,
Outputs Open,
V
CC
= 5.5V
V
IN
= 0V to V
CC
, tr = tf = 2.5 ns,
Outputs Open,
V
CC
= 5.5V
V
OUT
= GND, V
CC
= 5.5V
I
CCQT
50
70
85
100
mA
mA
mA
mA
mA
pF
pF
pF
Notes
1. 4.5V
≤
V
CC
≤
5.5V, –55°C
≤
T
C
≤
+125°C. Unless otherwise specified, testing shall be conducted at worst-case conditions.
2. V
IL
= –3.0V for pulse widths less than or equal to 20ns.
3. Duration of the short should not exceed one second; only one output may be shorted at a time.
Document #
MICRO-2
REV G
Page 4 of 25
PACE1750AE
SIGNAL PROPAGATION DELAYS
1,2
20 MHz
Symbol
Parameter
BUS REQ
BUS REQ
BUS GNT
setup
BUS GNT
hold
BUS BUSY
LOW
BUS BUSY
HIGH
BUS BUSY
setup
BUS BUSY
hold
BUS LOCK
LOW
BUS LOCK
HIGH
BUS LOCK
setup
Min
Max
30 MHz
Min
Max
40 MHz
Min
Max
Unit
t
C(BR)L
t
C(BR)H
t
BGV(C)
t
C(BG)X
t
C(BB)L
t
C(BB)H
t
BBV(C)
t
C(BB)X
t
C(BL)L
t
C(BL)H
t
BLV(C)
25
25
5
5
24
20
5
5
25
20
5
5
20
25
0
17
17
5
5
5
17
17
17
0
25
26
5
5
25
0
5
6
0
0
5
6
0
0
25
26
5
5
5
5
5
0
5
5
5
5
5
5
25
25
5
5
24
20
5
5
25
20
5
5
20
25
0
17
17
5
5
5
17
17
17
0
17
20
5
5
25
0
5
5
0
22
22
ns
ns
ns
ns
20
15
ns
ns
ns
ns
21
17
ns
ns
ns
ns
t
C(BL)X (IN)
BUS LOCK
hold
t
C(ST)V
t
C(ST)X
t
C(SA)H
t
C(SA)L
t
RAV(C)
t
C(RA)X
t
C(SDW)L
t
C(SD)H
D/
I
Status, AS
0
-AS
3
, AK
0
-AK
3
,
M/
IO
, R/
W
M/
IO
, R/
W
, D/
I
Status,
AS
0
-AS
3
, AK
0
-AK
3
STRBA HIGH
STRBA LOW
20
20
ns
ns
ns
16
16
ns
ns
ns
ns
ns
t
SAL(IBA)X
Address hold from STRBA LOW
RDYA setup
RDYA hold
STRBD
LOW write
STRBD
HIGH
14
14
14
ns
ns
ns
ns
ns
ns
ns
ns
t
FC(SDR)L
STRBD
LOW read
t
SDRH(IBD)X
STRBD
HIGH
t
SDWH(IBD)X
STRBD
HIGH
t
SDL(SD)H
STRBD
write
t
RDV(C)
t
C(RD)X
t
C(IBA)V
t
FC(IBA)X
t
C(IBD)X
t
C(IBD)X
RDYD setup
RDYD hold
IB
0
-IB
15
IB
0
-IB
15
20
ns
ns
ns
ns
ns
t
IBDRV(C)
IB
0
-IB
15
setup
IB
0
-IB
15
hold (read)
Data valid out (write)
Document #
MICRO-2
REV G
Page 5 of 25
stm32/stm8
