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P2082AF-08ST

Clock Generator, 156MHz, CMOS, PDSO8, SOIC-8

器件类别:嵌入式处理器和控制器    微控制器和处理器   

厂商名称:ALSC [Alliance Semiconductor Corporation]

器件标准:

下载文档
器件参数
参数名称
属性值
是否Rohs认证
符合
厂商名称
ALSC [Alliance Semiconductor Corporation]
零件包装代码
SOIC
包装说明
SOP,
针数
8
Reach Compliance Code
unknow
ECCN代码
EAR99
JESD-30 代码
R-PDSO-G8
JESD-609代码
e3/e6
长度
4.92 mm
端子数量
8
最高工作温度
70 °C
最低工作温度
最大输出时钟频率
156 MHz
封装主体材料
PLASTIC/EPOXY
封装代码
SOP
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE
峰值回流温度(摄氏度)
260
主时钟/晶体标称频率
78 MHz
认证状态
Not Qualified
座面最大高度
1.8 mm
最大供电电压
3.6 V
最小供电电压
3 V
标称供电电压
3.3 V
表面贴装
YES
技术
CMOS
温度等级
COMMERCIAL
端子面层
PURE MATTE TIN/TIN BISMUTH
端子形式
GULL WING
端子节距
1.27 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
40
宽度
3.95 mm
uPs/uCs/外围集成电路类型
CLOCK GENERATOR, OTHER
文档预览
October 2003
rev 0.4
Low Cost Frequency Multiplier
Features
Generates 2X and 4X clocks of the input clock
frequency
Input clock frequency range from 3 MHz to 78 MHz
Provides up to:
P2082A: 156 MHz output clock frequency
P2084A: 312 MHz output clock frequency
External loop filter
Low cycle-to-cycle jitter
3.3 V operating voltage range
10 mA output drives
TTL or CMOS compatible outputs
Ultra-low power CMOS design
Available in industrial temperature range
(-25C to +85C)
Available in 8-pin SOIC and TSSOP
P2082A
P2084A
multipliers that are designed specifically as cost effective
alternatives to the high precision frequency oscillator.
The P2082A/84A can generate a 2X and 4X output clock
respectively of the input frequency which allows system
cost savings by using an inexpensive crystal or resonator
to achieve high frequency multiplication.
The P2082A/84A provides up to 156 MHz and 312 MHz
output clock frequencies respectively through the use of the
Phase-Lock-Loop (PLL) technique which delivers low jitter
and high precision synthesized clocks.
Applications
The P2082A/84A is targeted towards the high frequency
CAN OSC replacement market. Applications include xDSL,
routers, networking, PC peripherals, and embedded
systems.
Product Description
The
P2082A
and
P2084A
are
versatile
frequency
Block Diagram
Alliance Semiconductor
2575, Augustine Drive
Santa Clara, CA
Tel: 408.855.4900
Fax: 408.855.4999
www.alsc.com
Notice: The information in this document is subject to change without notice.
October 2003
rev 0.4
Pin Configuration
P2082A
P2084A
Pin Description
Pin#
1
2
3
4
5
6
7
8
Pin Name
XIN/CLKIN
XOUT
FS1
LF
VSS
CLKOUT
FS0
VDD
Type
I
I
I
I
P
O
I
P
Description
Connect to crystal or clock input.
Crystal output.
Digital logic input used to select input frequency range. (See Input
Frequency Selection.) This pin has an internal pull-up resistor.
External loop filter for the PLL. (See Loop Filter Selection Table for value.)
Ground connection. Connect to system ground.
Clock output.
Digital logic input used to select input frequency range. (See Input
Frequency Selection.) This pin has an internal pull-up resistor.
Connect to +3.3 V.
Input Frequency Selection
FS1
0
0
1
1
FS0
0
1
0
1
Input (MHz)
3 to 9
10 to 19
20 to 38
39 to 78
Output Frequency Scaling
P2082A
P2084A
6 to 18
12 to 36
20 to 38
40 to 76
78 to 156
40 to 76
80 to 152
156 to 312
Low Cost Frequency Multiplier
Notice: The information in this document is subject to change without notice.
2 of 9
October 2003
rev 0.4
Loop Filter Selection Table VDD 3.3 V
P2082A
P2084A
Input (MHz)
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21 - 22
23 - 24
25 - 26
27 - 28
29 - 30
31 - 32
33 - 34
35 - 36
37 - 38
39 - 42
43 - 46
47 - 50
51 - 54
55 - 58
59 - 62
63 - 66
67 - 70
71 - 74
75 - 78
FS1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
FS0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
C1(pF)
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
270
C2(pF)
330,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
100,000
R1 (ohms)
220
270
390
510
620
820
1,000
330
390
510
560
620
750
820
910
1,000
1,200
330
390
510
560
620
750
820
910
1,000
1,200
330
390
510
560
620
750
820
910
1,000
1,200
Low Cost Frequency Multiplier
Notice: The information in this document is subject to change without notice.
3 of 9
October 2003
rev 0.4
Output Clock Selection Example
P2082A
P2084A
The P2084A can generate 4X from the input reference frequency. P2084A’s internal crystal oscillator circuits
allow the use of an inexpensive crystal of resonator to replace expensive can oscillators that are used in
networking, PC peripherals, xDSL, and consumer applications for high frequency generation. Its input frequency
range is optimized for operation from 3 MHz to 78 MHz, and its output frequency can deliver up to 312 MHz.
Low Cost Frequency Multiplier
Notice: The information in this document is subject to change without notice.
4 of 9
October 2003
rev 0.4
Absolute Maximum Ratings
Symbol
V
DD
, V
IN
T
STG
T
A
Parameter
Voltage on any pin with respect to GND
Storage temperature
Operating temperature
Rating
-0.5 to + 7.0
-65 to +125
0 to 70
P2082A
P2084A
Unit
V
°C
°C
DC Electrical Characteristics
Symbol
V
IL
V
IH
I
IL
I
IH
I
XOL
I
XOH
V
OL
V
OH
I
DD
I
CC
V
DD
t
ON
Z
OUT
Input low voltage
Input high voltage
Input low current (internal input pull-up resistor on FS0
and FS1)
Input high current (internal input pull-up resistor on FS0
and FS1)
XOUT output low current
XOUT output high current
Output low voltage (V
DD
= 3.3 V, I
OL
= 20 mA)
Output high voltage (V
DD
= 3.3 V, I
OH
= 20 mA)
Static supply current
Typical dynamic supply current (25 pF scope probe
loading)
Operating voltage
Power-up time (C
LOOP
= 0.1 µF at 16 MHz, first locked
cycle after power up)
Clock output impedance (at 16 MHz)
Parameter
Min
GND - 0.3
2.0
2.5
5.2 at 3
MHz
3.0
Typ
60
0
10
10
3
Max
0.8
V
DD
+
0.3
0.4
21.2 at
82 MHz
3.6
Unit
V
V
µA
µA
mA
mA
V
V
mA
mA
V
mS
3.3
7
28
AC Electrical Characteristics
Symbol
f
IN
f
OUT
t
LH
1
t
HL
t
D
1
Parameter
Input frequency
P2082A
P2084A
Output rise time (measured at 0.8 V to 2.0 V)
Output fall time (measured at 2.0 V to 0.8 V)
Jitter (cycle to cycle)
Output duty cycle
Min
3
6
12
Typ
1
1
Max
78
156
312
Unit
MHz
MHz
MHz
ns
ns
t
JC
45
±200
50
55
ps
%
1 t
LH
and t
HL
are measured into a capacitive load of 15 pF
Low Cost Frequency Multiplier
Notice: The information in this document is subject to change without notice.
5 of 9
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