P4C1024
P4C1024
HIGH SPEED 128K x 8
CMOS STATIC RAM
FEATURES
High Speed (Equal Access and Cycle Times)
— 15/17/20/25/35 ns (Commercial)
— 20/25/35/45 ns (Industrial)
Single 5 Volts
±
10% Power Supply
Easy Memory Expansion Using
CE
1,
CE
2
and
OE
Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Fast t
OE
Automatic Power Down
Packages
—32-Pin 300 mil DIP and SOJ
—32-Pin 400 mil SOJ
DESCRIPTION
The P4C1024 is a 1,048,576-bit high-speed CMOS
static RAM organized as 128Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
The P4C1024 device provides asynchronous opera-
tions with matching access and cycle times. Memory
locations are specified on address pins A
0
to A
16
. Read-
ing is accomplished by device selection (CE
1
low and
CE
2
high) and output enabling (OE) while write enable
(WE) remains HIGH. By presenting the address under
these conditions, the data in the addressed memory
Access times of 15 nanoseconds permit greatly en- location is presented on the data input/output pins. The
hanced system operating speeds. CMOS is utilized to input/output pins stay in the HIGH Z state when either
reduce power consumption to a low level. The P4C1024
CE
1
or
OE
is HIGH or
WE
or CE
2
is LOW.
is a member of a family of PACE RAM™ products offer-
ing fast access times.
Package options for the P4C1024 include 32-pin 300
mil DIP and SOJ packages as well as 400 mil SOJ.
FUNCTIONAL BLOCK DIAGRAM
ROW SELECT
A
•••
PIN CONFIGURATION
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
1024.2
(9)
A
262,144-
BIT
MEMORY
ARRAY
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
I/O
1
••• •••
••• •••
••• •••
INPUT
DATA
CONTROL
COLUMN
I/O
I/O
2
COLUMN
SELECT
WE
CE1
CE2
OE
CONTROL
CIRCUIT
A
•••
•••
GND
A
1024.1
(8)
DIP (P300), SOJ (J300, J400)
TOP VIEW
Means Quality, Service and Speed
1Q97
141
P4C1024
RECOMMENDED OPERATING TEMPERATURE & SUPPLY VOLTAGE
Temperature Range (Ambient)
Commercial (0°C to 70°C)
Industrial (-40°C to 85°C)
Supply Voltage
4.5V
≤
V
CC
≤
5.5V
4.5
≤
V
CC
≤
5.5V
MAXIMUM RATINGS
Stresses greater than those listed can cause permanent damage to the device. These are absolute stress
ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those
given in the operational sections of this data sheet. Exposure to Maximum Ratings for extended periods can
adversely affect device reliability.
Symbol
V
CC
V
TERM
T
A
S
TG
I
OUT
I
LAT
Parameter
Supply Voltage with Respect to GND
Terminal Voltage with Respect to GND (up to 7.0V)
Operating Ambient Temperature
Storage Temperature
Output Current into Low Outputs
Latch-up Current
>200
Min
-0.5
-0.5
-55
-65
Max
7.0
V
CC
+ 0.5
125
150
25
Unit
V
V
°C
°C
mA
mA
DC ELECTRICAL CHARACTERISTICS
(Over Recommended Operating Temperature & Supply Voltage)
Symbol
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
I
OS
Parameter
Output High Voltage
(I/O
0
- I/O
7
)
Output Low Voltage
(I/O
0
- I/O
7
)
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage Current
Output Short-Circuit
Current
V
CC
Current
CMOS Standby Current
(CMOS Input Levels)
GND
≤
V
IN
≤
V
CC
GND
≤
V
OUT
≤
V
CC
CE
1
≥
V
IH
or CE
2
≤
V
IL
Ind'l.
Com'l.
Ind'l.
Com'l.
Test Conditions
I
OH
= –4mA, V
CC
= 4.5V
I
OL
= 8 mA
I
OL
= 10 mA
2.2
-0.5
-10
-5
-10
-5
Min
2.4
0.4
0.5
V
CC
+ 0.3
0.8
+10
+5
+10
+5
-350
Max
Unit
V
V
V
V
V
µA
µA
mA
V
OUT
= GND, V
CC
= Max (Single
output) not to exceed 30 second
duration
V
CC
= 5.5V, I
OUT
= 0 mA
CE
1
≥
V
CC
-0.2V, CE
2
≤
0.2V
I
SB1
20
(Standard)
mA
142
P4C1024
CAPACITANCES
(V
CC
= 5.0V, T
A
= 25°C, f = 1.0 MHz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Test Conditions
V
IN
= 0V
V
OUT
= 0V
Max
8
10
Unit
pF
pF
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol
I
CC
Parameter
Dynamic Operating Current
Temperature
Range
Commercial
Industrial
-15
190
N/A
-17
180
N/A
-20
160
175
-25
150
165
-35
145
160
-45
N/A
155
Unit
mA
mA
*Tested
with outputs open and all address and data inputs changing at the maximum write-cycle rate.
The device is continuously enabled for writing, i.e., CE
2
≥
V
IH
(min),
CE
1
, and
WE
≤
V
IL
(max). Switching inputs are 0V
and 3V.
AC ELECTRICAL CHARACTERISTICS - READ CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
Symbol
t
RC
t
AA
t
AC
t
OH
t
LZ
t
HZ
t
OE
t
OLZ
t
OHZ
t
PU
t
PD
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access
Time
Output Hold from
Address Change
Chip Enable to
Output in Low Z
Chip Disable to
Output in High Z
Output Enable Low
to Data Valid
Output Enable Low
to Low Z
Output Enable High
to High Z
Chip Enable to
Power Up Time
Chip Disable to
Power Down Time
0
12
0
6
0
15
-35
-45
-15
-17
-20
-25
Min Max Min Max Min Max Min Max Min Max Min Max
15
15
15
3
3
8
6
0
7
0
20
3
3
9
7
0
9
0
20
17
17
17
3
3
9
9
0
11
0
20
20
20
20
3
3
11
10
0
15
0
25
25
25
25
3
3
15
15
0
20
35
35
35
3
3
20
20
45
45
45
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
143
P4C1024
READ CYCLE NO. 1 (OE CONTROLLED)
(1)
OE
t
RC
(5)
ADDRESS
tAA
OE
t OE
t
OH
t
CE
OLZ
CE 2
t
AC
t
LZ
DATA OUT
t
OHZ
t
HZ
NOTES:
1.
WE
is HIGH for READ cycle.
2.
CE
1
and
OE
is LOW and CE
2
is HIGH for read cycle.
3. ADDRESS must be valid prior to, or coincident with later of
CE
1
transition LOW or CE
2
transition HIGH.
4. Transition is measured
±
200 mV from steady state voltage
prior to change, with loading as specified in Figure1. This
parameter is sampled and not 100% tested.
5. READ Cycle Time is measured from the last valid address to
the first transitioning address.
READ CYCLE NO. 2 (ADDRESS CONTROLLED)
t
RC (5)
ADDRESS
t
AA
t
OH
DATA OUT
PREVIOUS DATA VALID
DATA VALID
READ CYCLE NO. 3 (CE CONTROLLED)
CE
tRC
CE
1
CE
2
tAC
tLZ
DATA OUT
ICC
VCC SUPPLY I
SB
CURRENT
tPU
DATA VALID
HIGH IMPEDANCE
tPD
tHZ
144
P4C1024
AC CHARACTERISTICS - WRITE CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
Symbol
t
WC
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
OW
Parameter
Write Cycle Time
Chip Enable Time
to End of Write
Address Valid to
End of Write
Address Set-up
Time
Write Pulse Width
Address Hold Time
Data Valid to End
of Write
Data Hold Time
Write Enable to
Output in High Z
Output Active from
End of Write
3
-15
-17
-45
-25
-20
-35
Unit
Min Max Min Max Min Max Min Max Min Max Min Max
15
12
12
0
12
0
7
0
8
3
17
13
13
0
12
0
7
0
8
3
20
15
15
0
15
0
8
0
10
3
25
18
20
0
18
0
10
0
11
3
35
22
25
0
22
0
15
0
15
3
45
30
35
0
25
0
20
0
18
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WRITE CYCLE NO. 1 (WE CONTROLLED)
(6)
WE
t
WC
ADDRESS
t
CW
CE
1
(9)
CE
2
t
AW
t
WP
WE
t
AS
DATA IN
t
WZ
DATA OUT
(7)
(4)
t
AH
t
DW
DATA VALID
t
DH
t
OW
(4,7)
DATA UNDEFINED
HIGH IMPEDANCE
Notes:
6.
CE
1
and
WE
are LOW and CE
2
is HIGH for WRITE cycle.
7.
OE
is LOW for this WRITE cycle to show twz and tow.
8. If
CE
1
goes HIGH or CE
2
goes LOW simultaneously with
WE
HIGH, the output remains in a high impedance state.
9. Write Cycle Time is measured from the last valid address to the first transitioning address.
145
