P4C1256
HIGH SPEED 32K x 8
STATIC CMOS RAM
FEATURES
High Speed (Equal Access and Cycle Times)
— 12/15/20/25/35 ns (Commercial)
— 15/20/25/35/45 ns (Industrial)
— 20/25/35/45/55/70 ns (Military)
Low Power
Single 5V±10% Power Supply
Easy Memory Expansion Using
CE
and
OE
Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Fast t
OE
Automatic Power Down
Packages
—28-Pin 300 mil DIP, SOJ, TSOP
—28-Pin 300 mil Ceramic DIP
—28-Pin 600 mil Ceramic DIP
—28-Pin CERPACK
—28-Pin SOP
—28-Pin LCC (350 mil x 550 mil)
—32-Pin LCC (450 mil x 550 mil)
DESCRIPTION
The P4C1256 is a 262,144-bit high-speed CMOS
static RAM organized as 32Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times as fast as 12 nanoseconds permit greatly
enhanced system operating speeds. CMOS is utilized
to reduce power consumption to a low level. The
P4C1256 is a member of a family of PACE RAM™ prod-
ucts offering fast access times.
The P4C1256 device provides asynchronous operation
with matching access and cycle times. Memory loca-
tions are specified on address pins A
0
to A
14
. Reading
is accomplished by device selection (CE and output
enabling (OE) while write enable (WE) remains HIGH.
By presenting the address under these conditions, the
data in the addressed memory location is presented on
the data input/output pins. The input/output pins stay
in the HIGH Z state when either
CE
or
OE
is HIGH or
WE
is LOW.
Package options for the P4C1256 include 28-pin 300
mil DIP, SOJ and TSOP packages. For military tempera-
ture range, Ceramic DIP and LCC packages are avail-
able.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
DIP (P5, C5, C5-1, D5-2), SOJ (J5), SOP (S11-1, S11-3)
CERPACK (F4) SIMILAR
1519B
See end of datasheet for LCC and TSOP
pin configurations.
Document #
SRAM119
REV G
1
Revised June 2007
P4C1256
MAXIMUM RATINGS
(1)
Symbol
V
CC
Parameter
Power Supply Pin with
Respect to GND
Terminal Voltage with
Respect to GND
(up to 7.0V)
Operating Temperature
Value
–0.5 to +7
–0.5 to
V
CC
+0.5
–55 to +125
Unit
V
Symbol
T
BIAS
T
STG
V
°C
P
T
I
OUT
Parameter
Temperature Under
Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
–55 to +125
–65 to +150
1.0
50
Unit
°C
°C
W
mA
V
TERM
T
A
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade(2)
Military
Ambient
Temperature
GND
0V
0V
0V
V
CC
5.0V ± 10%
5.0V ± 10%
5.0V ± 10%
CAPACITANCES
(4)
V
CC
= 5.0V, T
A
= 25°C, f = 1.0MHz
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Conditions Typ. Unit
V
IN
= 0V
8
10
pF
pF
–55°C to +125°C
–40°C to +85°C
Industrial
Commercial
0°C to +70°C
Output Capacitance V
OUT
= 0V
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage
(2)
Symbol
V
IH
V
IL
V
HC
V
LC
V
OL
V
OH
Parameter
Input High Voltage
Input Low Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
Output Low Voltage
(TTL Load)
Output High Voltage
(TTL Load)
Input Leakage Current
I
OL
= +8 mA, V
CC
= Min.
I
OH
= –4 mA, V
CC
= Min.
V
CC
= Max.
V
IN
= GND to V
CC
V
CC
= Max.,
I
LO
Output Leakage Current
CE
= V
IH
,
V
OUT
= GND to V
CC
CE
≥
V
IH
I
SB
Mil.
___
___
45
30
___
___
30
n/a
mA
Mil.
Ind./Com’l.
Mil.
Ind./Com’l.
2.4
–10
–5
–10
–5
+10
+5
+10
+5
Test Conditions
P4C1256
Min
Max
V
CC
+0.5
2.2
P4C1256L
Unit
Min
Max
V
CC
+0.5 V
2.2
V
V
V
V
V
+5
n/a
+5
n/a
µA
µA
0.8
0.8
–0.5
(3)
–0.5
(3)
V
CC
–0.2 V
CC
+0.5 V
CC
–0.2 V
CC
+0.5
–0.5
(3)
0.2
0.4
2.4
–5
n/a
–5
n/a
–0.5
(3)
0.2
0.4
I
LI
Standby Power Supply
V
CC
= Max,
Ind./Com’l.
Current (TTL Input Levels) f = Max., Outputs Open
CE
≥
V
HC
I
SB1
Standby Power Supply
Current
(CMOS Input Levels)
V
CC
= Max,
f = 0, Outputs Open
V
IN
≤
V
LC
or V
IN
≥
V
HC
Mil.
Ind./Com’l.
___
___
20
10
___
___
10
n/a
mA
N/A = Not Applicable
Document #
SRAM119
REV G
Page 2 of 17
P4C1256
DATA RETENTION CHARACTERISTICS (P4C1256L Military Temperature Only)
Symbol
V
DR
I
CCDR
t
CDR
t
R †
*T
A
= +25°C
§t
RC
= Read Cycle Time
†
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to
Data Retention Time
Operation Recovery Time
Test Conditons
Min
2.0
Typ.*
V
CC
=
2.0V
3.0V
Max
V
CC
=
2.0V
3.0V
Unit
V
CE
≥
V
CC
–0.2V,
V
IN
≥
V
CC
–0.2V
or V
IN
≤
0.2V
0
t
RC§
10
15
100
200
µA
ns
ns
This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol
Parameter
Temperature
Range
Commercial
Military
–12
170
N/A
N/A
–15
160
170
N/A
–20
155
165
170
–25
150
160
165
–35
145
155
160
–45
N/A
150
155
–55
N/A
N/A
150
–70
N/A
N/A
150
Unit
mA
mA
mA
I
CC
Dynamic Operating Current* Industrial
*V
CC
= 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V.
CE
= V
IL
,
OE
= V
IH
.
Document #
SRAM119
REV G
Page 3 of 17
P4C1256
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Sym.
t
RC
t
AA
t
AC
t
OH
t
LZ
t
HZ
t
OE
Parameter
Read Cycle Time
Address Access
Time
Chip Enable
Access Time
Output Hold from
Address Change
Chip Enable to
Output in Low Z
Chip Disable to
Output in High Z
Output Enable
Low to Data
Valid
Output Enable
Low to Low Z
Output Enable
High to High Z
Chip Enable to
Power Up Time
Chip Disable to
Power Down
Time
0
0
2
2
-12
12
12
12
2
2
5
5
-15
15
15
15
2
2
8
7
20
-20
25
20
20
3
3
9
9
-25
35
25
25
3
3
11
10
-35
45
35
35
3
3
15
15
-45
55
45
45
3
3
20
20
-55
70
55
55
3
3
25
25
-70
Unit
ns
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
70
70
ns
ns
ns
ns
30
30
ns
ns
t
OLZ
t
OHZ
t
PU
t
PD
0
5
0
12
15
7
0
9
0
20
0
11
0
20
0
15
0
20
0
20
0
25
0
25
0
30
0
30
0
35
ns
ns
ns
ns
Document #
SRAM119
REV G
Page 4 of 17
P4C1256
TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)
(5)
OE
TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)
(5,6)
TIMING WAVEFORM OF READ CYCLE NO. 3 (CE CONTROLLED)
(5,7)
CE
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
5.
WE
is HIGH for READ cycle.
6.
CE
is LOW and
OE
is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with
CE
transition LOW.
8. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
Document #
SRAM119
REV G
Page 5 of 17
