P4C1258
ULTRA HIGH SPEED 64K x 4
STATIC CMOS RAM
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 15/20/25/35 ns (Commercial/Industrial)
Low Power
Single 5V±10% Power Supply
Data Retention with 2.0V Supply
Three-State Outputs
TTL/CMOS Compatible Outputs
Fully TTL Compatible Inputs
Standard Pinout (JEDEC Approved)
– 24-Pin 300 mil DIP, SOJ
DESCRIPTION
The P4C1258 is a 262,144-bit ultra high speed static RAM
organized as 64K x 4. The CMOS memory requires no clock
or refreshing and has equal access and cycle times. Inputs
and outputs are fully TTL-compatible. The RAM operates
from a single 5V±10% tolerance power supply. With battery
backup, data integrity is maintained for supply voltages
down to 2.0V. Current drain is typically 10 µA from a 2.0V
supply.
Access times as fast as 15 nanoseconds are available,
permitting greatly enhanced system speeds. CMOS is
utilized to reduce power consumption.
The P4C1258 is available in a 24-pin 300 mil DIP or SOJ
packages providing excellent board level densities.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
DIP (P4)
SOJ (J4)
Document #
SRAM123
REV OR
1
Revised October 2005
P4C1258
MAXIMUM RATINGS
(1)
Symbol
V
CC
Parameter
Power Supply Pin with
Respect to GND
Terminal Voltage with
Respect to GND
(up to 7.0V)
Operating Temperature
Value
–0.5 to +7
–0.5 to
V
CC
+0.5
–55 to +125
Unit
V
Symbol
T
BIAS
T
STG
P
T
I
OUT
Parameter
Temperature Under
Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
–55 to +125
–65 to +150
1.0
50
Unit
°C
°C
W
mA
V
TERM
T
A
V
°C
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade(2)
Industrial
Commercial
Ambient
Temperature
–40°C to +85°C
0°C to +70°C
GND
0V
0V
V
CC
5.0V ± 10%
5.0V ± 10%
CAPACITANCES
(4)
V
CC
= 5.0V, T
A
= 25°C, f = 1.0MHz
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions Typ. Unit
V
IN
= 0V
V
OUT
= 0V
5
7
pF
pF
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage
(2)
Symbol
V
IH
V
IL
V
HC
V
LC
V
CD
V
OL
V
OH
I
LI
I
LO
I
SB
I
SB1
Parameter
Input High Voltage
Input Low Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
Input Clamp Diode Voltage V
CC
= Min., I
IN
= 18 mA
Output Low Voltage
(TTL Load)
Output High Voltage
(TTL Load)
Input Leakage Current
Output Leakage Current
I
OL
= +8 mA, V
CC
= Min.
I
OH
= –4 mA, V
CC
= Min.
V
CC
= Max.
V
IN
= GND to V
CC
V
CC
= Max.,
CE
= V
IH
V
OUT
= GND to V
CC
2.4
–5
–5
___
___
+5
+5
35
10
Test Conditions
P4C1258
Min
Max
2.2
–0.5
(3)
–0.5
(3)
V
CC
+0.5
0.8
0.2
–1.2
0.4
Unit
V
V
V
V
V
V
V
µA
µA
mA
V
CC
–0.2 V
CC
+0.5
CE
≥
V
IH
Standby Power Supply
Current (TTL Input Levels) V
CC
= Max ., f = Max., Outputs Open
Standby Power Supply
Current
(CMOS Input Levels)
CE
≥
V
HC
V
CC
= Max., f = 0, Outputs Open
V
IN
≤
V
LC
or V
IN
≥
V
HC
mA
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
Document #
SRAM123
REV OR
Page 2 of 9
P4C1258
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol
I
CC
Parameter
Dynamic Operating Current*
Temperature
Range
Commercial
Industrial
–15
160
170
–20
125
135
–25
115
120
–35
110
115
Unit
mA
mA
*V
CC
= 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V.
CE
= V
IL
DATA RETENTION CHARACTERISTICS
Symbol
V
DR
I
CCDR
t
CDR
t
R†
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to
Data Retention Time
Operation Recovery Time
CE
≥
V
CC
–0.2V,
V
IN
≥
V
CC
–0.2V or
V
IN
≤
0.2V
Test Conditions
Min
2.0
10
0
t
RC§
15
1500
2000
Typ.*
V
CC
=
2.0V
3.0V
Max
V
CC
=
2.0V 3.0V
Unit
V
µA
ns
ns
*T
A
= +125°C
§
†
t
RC
= Read Cycle Time
This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
Document #
SRAM123
REV OR
Page 3 of 9
P4C1258
AC CHARACTERISTICS—READ CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Sym.
t
RC
t
AA
t
AC
t
OH
t
LZ
t
HZ
t
PU
t
PD
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Hold from Address Change
Chip Enable to Output in Low Z
Chip Disable to Output in High Z
Chip Enable to Power Up Time
Chip Disable to Power Down Time
-15
Min
15
15
15
2
2
8
0
15
0
2
3
Max
-20
Min Max
20
20
20
2
3
9
0
20
Min
25
-25
Max
25
25
2
3
10
0
25
35
-35
Min
Max
35
35
Unit
ns
ns
ns
ns
ns
ns
ns
ns
11
35
TIMING WAVEFORM OF READ CYCLE NO. 1
(5)
TIMING WAVEFORM OF READ CYCLE NO. 2
(6)
Notes:
5.
CE
is LOW and
WE
is HIGH for READ cycle.
6.
WE
is HIGH, and address must be valid prior to or coincident with
CE
transition LOW.
7. Transition is measured ±200mV from steady state voltage prior to
change with specified loading in Figure 1. This parameter is sampled
and not 100% tested.
8. Read Cycle Time is measured from the last valid address to the first
transitioning address.
Document #
SRAM123
REV OR
Page 4 of 9
P4C1258
AC CHARACTERISTICS - WRITE CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Sym.
t
WC
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
DW
Parameter
Write Cycle Time
Chip Enable Time to End of Write
Address Valid to End of Write
Address Set-up Time
Write Pulse Width
Address Hold Time from End of Write
Data Valid to End of Write
Data Hold Time
Write Enable to Output in High Z
Output Active from End of Write
2
-15
13
12
12
0
12
0
7
0
6
2
20
15
15
0
15
0
8
0
8
2
-20
25
18
18
0
18
0
10
0
10
3
-25
35
25
25
0
25
0
15
0
15
-35
Min Max Min Max Min Max Min Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)
(9)
WE
Notes:
9.
CE
and
WE
must be LOW for WRITE cycle.
10. If
CE
goes HIGH simultaneously with
WE
HIGH, the output remains
in a high impedance state.
11. Write Cycle Time is measured from the last valid address to the first
transition address.
12. Transition is measured ±200mV from steady state voltage prior to
change with specified loading in Figure 1. This parameter is
sampled and not 100% tested.
Document #
SRAM123
REV OR
Page 5 of 9
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