P4C164
ULTRA HIGH SPEED 8K X 8
STATIC CMOS RAMS
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 8/10/12/15/20/25/35/70/100 ns (Commercial)
– 10/12/15/20/25/35/70/100 ns(Industrial)
– 12/15/20/25/35/45/70/100 ns (Military)
Low Power Operation
Output Enable and Dual Chip Enable Control
Functions
Single 5V±10% Power Supply
Data Retention with 2.0V Supply, 10 µA Typical
Current (P4C164L Only)
Common Data I/O
Fully TTL Compatible Inputs and Outputs
Standard Pinout (JEDEC Approved)
– 28-Pin 300 mil Plastic DIP, SOJ
– 28-Pin 600 mil Plastic DIP
– 28-Pin 300 mil SOP (70 & 100ns)
– 28-Pin 300 mil Ceramic DIP
– 28-Pin 600 mil Ceramic DIP
– 28-Pin 350 x 550 mil LCC
– 32-Pin 450 x 550 mil LCC
– 28-Pin Glass-sealed CERPACK
– 28-Pin Solder-sealed CERPACK
DESCRIPTIOn
The P4C164 is a 65,536-bit ultra high-speed static RAM
organized as 8K x 8. The CMOS memory requires no
clocks or refreshing and has equal access and cycle times.
Inputs are fully TTL-compatible. The RAM operates from
a single 5V±10% tolerance power supply. With battery
backup (P4C164L Only), data integrity is maintained with
supply voltages down to 2.0V. Current drain is typically 10
µA from a 2.0V supply.
Access times as fast as 8 nanoseconds are available,
permitting greatly enhanced system operating speeds.
The P4C164 is available in 28-pin 300 mil DIP and SOJ,
28-pin 600 mil plastic and ceramic DIP, 28-pin 350 x 550 mil
LCC, 32-pin 450 x 550 mil LCC, and 28-pin glass-sealed
CERPACK and solder-sealed flatpack.
FUnCTIOnAL BLOCK DIAGRAM
PIn COnFIGURATIOnS
DIP (P5, P6, C5, C5-1, D5-1, D5-2),
SOJ (J5), CERPACK (F4), SOLDER-SEAL FLATPACK (FS-5), SOP (S6)
SEE PAGE 8 FOR LCC PIN CONFIGURATIONS
Document #
SRAM115
REV H
Revised April 2011
P4C164 - ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAM
MAxIMUM RATInGS
(1)
Sym
V
CC
V
TERM
T
A
T
BIAS
T
STG
P
T
I
OUT
Parameter
Power Supply Pin with
Respect to GND
Terminal Voltage with
Respect to GND (up to
7.0V)
Operating Temperature
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
-0.5 to +7
-0.5 to VCC + 0.5
-55 to +125
-55 to +125
-65 to +150
1.0
50
Unit
V
V
°C
°C
°C
W
mA
RECOMMEnDED OPERATInG COnDITIOnS
Grade
(2)
Commercial
Industrial
Military
Ambient Temp
0°C to 70°C
-40°C to +85°C
-55°C to +125°C
GnD
0V
0V
0V
V
CC
5.0V ± 10%
5.0V ± 10%
5.0V ± 10%
CAPACITAnCES
(4)
Sym
C
IN
C
OUT
Parameter
(V
CC
= 5.0V, T
A
= 25°C, f = 1.0MHz)
Conditions
V
IN
=0V
V
OUT
=0V
Typ
5
7
Unit
pF
pF
Input Capacitance
Output Capacitance
DC ELECTRICAL CHARACTERISTICS
Sym Parameter
V
IH
V
IL
V
HC
V
LC
V
CD
V
OL
V
OH
I
LI
Input High Voltage
Input Low Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
Input Clamp Diode Voltage
Output Low Voltage (TTL Load)
Output High Voltage (TTL Load)
Input Leakage Current
(Over Recommended Operating Temperature & Supply Voltage)
(2)
Test Conditions
P4C164
Min
2.2
-0.5
(3)
V
CC
- 0.2
-0.5
(3)
V
CC
= Min, I
IN
= -18 mA
I
OL
= +8 mA, V
CC
= Min
I
OH
= -4 mA, V
CC
= Min
V
CC
= Max,
V
IN
= GND to V
CC
V
CC
= Max,
CE
1
= V
IH
,
V
OUT
= GND to V
CC
CE
1
≥ V
IH
or CE
2
≤ V
IL
,
V
CC
=Max, f=Max, Outputs Open
CE
1
≥ V
HC
or CE
2
≤ V
LC
,
V
CC
= Max, f = 0, Outputs Open
V
IN
≤ V
LC
or V
IN
≥ V
HC
IND/COM
—
15
—
N/A
MIL
IND/COM
MIL
IND/COM
MIL
IND/COM
MIL
2.4
-10
-5
-10
-5
—
—
—
+10
+5
+10
+5
40
30
25
P4C164L
Min
2.2
-0.5
(3)
V
CC
- 0.2
-0.5
(3)
Max
V
CC
+ 0.5
0.8
V
CC
+ 0.5
0.2
-1.2
0.4
Max
V
CC
+ 0.5
0.8
V
CC
+ 0.5
0.2
-1.2
0.4
Unit
V
V
V
V
V
V
V
2.4
-5
N/A
-5
N/A
—
—
—
+5
N/A
+5
N/A
40
N/A
1
µA
I
LO
Output Leakage Current
µA
I
SB
Standby Power Supply Current
(TTL Input Levels)
mA
I
SB1
Standby Power Supply Current
(CMOS Input Levels)
mA
N/A = Not applicable
notes:
1. Stresses greater than those listed under MAxIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAxIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
Document #
SRAM115
REV H
Page 2
P4C164 - ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAM
POWER DISSIPATIOn CHARACTERISTICS VS. SPEED
Sym
I
CC
Parameter
Dynamic
Operating
Current*
Temperature Range
Commercial
Industrial
Military
-8
200
N/A
N/A
-10
180
190
N/A
-12
170
180
180
-15
160
170
170
-20
155
160
160
-25
150
155
155
-35
145
150
150
-45
N/A
N/A
145
-70
130
145
145
-100
125
140
145
Unit
mA
mA
mA
* V
CC
= 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V.
CE
1
= V
IL
, CE
2
= V
IH
,
OE
= V
IH
.
DATA RETEnTIOn CHARACTERISTICS (P4C164L Only)
Sym
V
DR
I
CCDR
t
CDR
t
R†
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
CE
1
≥ V
CC
-0.2V or
CE
2
≤ 0.2V, V
IN
≥ V
CC
-0.2V
or V
IN
≤ 0.2V
0
t
RC§
Test Conditions
Min
2.0
10
15
200
300
Typ* V
CC
=
2.0V
3.0V
Max V
CC
=
2.0V
3.0V
Unit
V
µA
ns
ns
* T
A
= +25°C
§ t
RC
= Read Cycle Time
† This Parameter is guaranteed but not tested
DATA RETEnTIOn WAVEFORM
Document #
SRAM115
REV H
Page 3
P4C164 - ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAM
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Sym Parameter
t
RC
t
AA
t
AC
t
OH
t
LZ
t
HZ
t
OE
t
OLZ
t
OHZ
t
PU
t
PD
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Hold from Address Change
Chip Enable to Output in Low Z
Chip Disable to Output in High Z
Output Enable Low to Data Valid
Output Enable Low to Low Z
Output Enable High to High Z
Chip Enable to Power Up Time
Chip Disable to Power Down Time
-25
Min
25
25
25
3
2
10
13
2
12
0
20
0
20
2
15
0
25
3
2
15
18
2
20
0
35
Max
Min
35
35
35
3
2
20
20
2
35
0
45
0
8
-35
Max
Min
45
45
45
3
2
35
35
2
45
2
5
0
10
-45
Max
Min
70
70
70
3
2
45
45
3
2
5
5
2
6
0
12
-70
Max
-8
Min
8
8
8
3
2
6
6
2
7
0
15
-100
Min
100
100
100
Max
Max
Min
10
10
10
3
2
7
7
2
9
0
20
-10
Max
Min
12
12
12
3
2
8
9
2
9
-12
Max
Min
15
15
15
3
2
8
10
-15
Max
Min
20
20
20
-20
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Sym Parameter
t
RC
t
AA
t
AC
t
OH
t
LZ
t
HZ
t
OE
t
OLZ
t
OHZ
t
PU
t
PD
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Hold from Address Change
Chip Enable to Output in Low Z
Chip Disable to Output in High Z
Output Enable Low to Data Valid
Output Enable Low to Low Z
Output Enable High to High Z
Chip Enable to Power Up Time
Chip Disable to Power Down Time
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Document #
SRAM115
REV H
Page 4
P4C164 - ULTRA HIGH SPEED 8K x 8 STATIC CMOS RAM
TIMInG WAVEFORM OF READ CYCLE nO. 1 (OE COnTROLLED)
(5)
TIMInG WAVEFORM OF READ CYCLE nO. 2 (ADDRESS COnTROLLED)
(5,6)
TIMInG WAVEFORM OF READ CYCLE nO. 3 (CE
1
, CE
2
COnTROLLED)
(5,7,10)
5.
WE
is HIGH for READ cycle.
6.
CE
1
is LOW, CE
2
is HIGH and
OE
is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with
CE
1
transition LOW
and CE
2
transition HIGH.
8. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is sampled
and not 100% tested.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
10. Transitions caused by a chip enable control have similar delays ir-
respective of whether
CE
1
or CE
2
causes them.
Document #
SRAM115
REV H
Page 5
