P4C164/164L
P4C164/P4C164L
ULTRA HIGH SPEED 8K x 8
STATIC CMOS RAMS
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 8/10/12/15/20/25 ns (Commercial)
– 10/12/15/20/25/35 (Industrial)
– 12/15/20/25/35/45 ns (Military)
Low Power Operation
– 770mW Active –15
– 660/743 mW Active – 20
– 495/575 mW Active – 25, 35, 45
– 193/220 mW Standby (TTL Input)
– 5.5mW Standby (CMOS Input) P4C164L (Military)
Output Enable and Dual Chip Enable Control
Functions
Single 5V
±
10% Power Supply
Data Retention with 2.0V Supply, 10
µ
A Typical
Current (P4C164L Military)
Common Data I/O
Fully TTL Compatible Inputs and Outputs
Standard Pinout (JEDEC Approved)
– 28-Pin 300 mil DIP, SOJ
– 28-Pin 600 mil Ceramic DIP
– 28-Pin 350 x 550 mil LCC
– 28-Pin CERPACK
DESCRIPTION
The P4C164 and P4C164L are 65,536-bit ultra high-speed
static RAMs organized as 8K x 8. The CMOS memories
require no clocks or refreshing and have equal access and
cycle times. Inputs are fully TTL-compatible. The RAMs
operate from a single 5V±10% tolerance power supply.
With battery backup, data integrity is maintained with
supply voltages down to 2.0V. Current drain is typically 10
µA
from a 2.0V supply.
Access times as fast as 10 nanoseconds are available,
permitting greatly enhanced system operating speeds. In
full standby mode with CMOS inputs, power consumption
is only 5.5 mW for the P4C164L.
The P4C164 and P4C164L are available in 28-pin 300 mil
DIP and SOJ, 28-pin 600 mil ceramic DIP, and 28-pin 350
x 550 mil LCC packages providing excellent board level
densities.
FUNCTIONAL BLOCK DIAGRAM
A
0
••••••
PIN CONFIGURATIONS
V
CC
A
2
A
1
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
CE
2
A
12
A
11
A
10
OE
A
9
CE
1
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
1519B
ROW
SELECT
65,536-BIT
MEMORY
ARRAY
A
0
A
1
A
2
A
3
A
4
3
NC
A
3
A
4
A
5
A
6
A
7
A
8
I/O
1
I/O
2
4
5
6
7
8
9
10
11
12
13
I/O
3
A
0
2
A
7
I/O
1
•••
•••
•••
27
26
28
1
25
24
23
22
21
20
19
WE
CE
2
A
12
A
OE
A
9
CE
1
I/O
8
I/O
7
11
A
10
A
5
INPUT
DATA
CONTROL
A
6
A
7
A
8
I/O
1
I/O
2
I/O
3
COLUMN I/O
I/O
8
14 15 16
GND
I/O
4
I/O
5
18
17
I/O
6
CE
1
CE
2
WE
OE
A
8
COLUMN
SELECT
1519C
GND
••••••
1519A
A
12
DIP (P5, D5-2, D5-1), SOJ (J5)
CERPACK (F4) SIMILAR
TOP VIEW
1519B
LCC (L5)
TOP VIEW
Means Quality, Service and Speed
1Q97
91
P4C164/164L
MAXIMUM RATINGS
(1)
Symbol
V
CC
Parameter
Power Supply Pin with
Respect to GND
Terminal Voltage with
Respect to GND
(up to 7.0V)
Operating Temperature
Value
–0.5 to +7
–0.5 to
V
CC
+0.5
–55 to +125
Unit
V
Symbol
T
BIAS
T
STG
V
°C
P
T
I
OUT
Parameter
Temperature Under
Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
–55 to +125
–65 to +150
1.0
50
Unit
°C
°C
W
mA
V
TERM
T
A
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade(2)
Military
Industrial
Commercial
Ambient
Temperature
–55°C to +125°C
–40°C to +85°C
0°C to +70°C
GND
0V
0V
0V
V
CC
5.0V
±
10%
5.0V
±
10%
5.0V
±
10%
CAPACITANCES
(4)
V
CC
= 5.0V, T
A
= 25°C, f = 1.0MHz
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Conditions Typ. Unit
V
IN
= 0V
5
7
pF
pF
Output Capacitance V
OUT
= 0V
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage
(2)
Symbol
V
IH
V
IL
V
HC
V
LC
V
CD
V
OL
V
OH
I
LI
I
LO
I
SB
Parameter
Input High Voltage
Input Low Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
Input Clamp Diode Voltage V
CC
= Min., I
IN
= 18 mA
Output Low Voltage
(TTL Load)
Output High Voltage
(TTL Load)
Input Leakage Current
Output Leakage Current
I
OL
= +8 mA, V
CC
= Min.
I
OH
= –4 mA, V
CC
= Min.
V
CC
= Max.
V
IN
= GND to V
CC
V
CC
= Max.,
CE
= V
IH
,
V
OUT
= GND to V
CC
Mil.
Com’l.
Mil.
Com’l.
2.4
–10
–5
–10
–5
___
___
___
___
+10
+5
+10
+5
40
30
25
15
Test Conditions
P4C164
Min
Max
V
CC
+0.5
2.2
–0.5
(3)
–0.5
(3)
0.8
0.2
–1.2
0.4
2.4
–5
n/a
–5
n/a
___
___
___
___
+5
n/a
+5
n/a
40
n/a
1
n/a
P4C164L
Unit
Min
Max
2.2
V
CC
+0.5 V
–0.5
(3)
–0.5(3)
0.8
0.2
–1.2
0.4
V
V
V
V
V
V
µA
µA
mA
V
CC
–0.2 V
CC
+0.5 V
CC
–0.2 V
CC
+0.5
Standby Power Supply
CE
≥
V
IH
or
Mil.
Current (TTL Input Levels) CE
2
≤V
IL
, V
CC
= Max Ind./Com’l.
f = Max., Outputs Open
Standby Power Supply
Current
(CMOS Input Levels)
CE
≥
V
HC
or
Mil.
CE
2
≤V
LC
, V
CC
= Max Ind./Com’l.
f = 0, Outputs Open
V
IN
≤
V
LC
or V
IN
≥
V
HC
I
SB1
mA
n/a = Not Applicable
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
92
P4C164/164L
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol
Parameter
Temperature
Range
Commercial
I
CC
Dynamic Operating Current* Industrial
Military
–8
200
N/A
N/A
–10
180
190
N/A
–12
170
180
180
–15
160
170
170
–20
155
160
160
–25
150
155
155
–35
N/A
150
150
–45
N/A
N/A
145
Unit
mA
mA
mA
*V
CC
= 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V.
CE
1
= V
IL
, CE
2
= V
IH
,
OE
= V
IH
DATA RETENTION CHARACTERISTICS (P4C164L, Military Temperature Only)
Symbol
V
DR
I
CCDR
t
CDR
t
R†
*
T
A
= +25°C
§
†
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to
Data Retention Time
Operation Recovery Time
Test Condition
Min
2.0
Typ.*
V
CC
=
2.0V
3.0V
10
15
Max
V
CC
=
2.0V
3.0V
200
300
Unit
V
µA
ns
ns
CE
1
≥
V
CC
– 0.2V or
CE
2
≤
0.2V, V
IN
≥
V
CC
– 0.2V
or V
IN
≤
0.2V
0
t
RC§
t
RC
= Read Cycle Time
This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
DATA RETENTION MODE
V
CC
t
CDR
CE
1
V
DR
V
HC
V
LC
V
HC
V
LC
4.5V
V
DR
≥
2V
4.5V
t
R
CE
2
93
P4C164/164L
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(V
CC
= 5V
±
10%, All Temperature Ranges)
(2)
Sym.
t
RC
t
AA
t
AC
t
OH
t
LZ
t
HZ
t
OE
Parameter
Read Cycle Time
Address Access
Time
Chip Enable
Access Time
Output Hold from
Address Change
Chip Enable to
Output in Low Z
Chip Disable to
Output in High Z
Output Enable
Low to Data
Valid
Output Enable
Low to Low Z
Output Enable
High to High Z
Chip Enable to
Power Up Time
Chip Disable to
Power Down
Time
-8
8
8
8
3
2
5
5
3
2
-10
10
10
10
3
2
6
6
-12
12
12
12
3
2
7
7
-15
15
15
15
3
2
8
9
-20
20
20
20
3
2
8
10
-25
25
25
25
3
2
10
13
-35
35
35
35
3
2
15
18
-45
45
45
45
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
Unit
ns
ns
ns
ns
ns
20
20
ns
ns
t
OLZ
t
OHZ
t
PU
t
PD
2
5
0
8
2
6
0
10
2
7
0
12
2
9
0
15
2
9
0
20
2
12
0
20
2
15
0
20
2
20
0
25
ns
ns
ns
ns
READ CYCLE NO. 1 (OE CONTROLLED)
(5)
OE
t
RC
ADDRESS
t
AA
OE
t
OE
CE
1
t
OLZ
(8)
t
OH
(9)
CE
2
t
AC
t
LZ
(8)
DATA OUT
t
OHZ
(8)
t
HZ
(8)
Notes:
5.
WE
is HIGH for READ cycle.
6.
CE
1
is LOW, CE
2
is HIGH and
OE
is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with
CE
1
transition
LOW and CE
2
transition HIGH.
8. Transition is measured
±
200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
94
P4C164/164L
READ CYCLE NO. 2 (ADDRESS CONTROLLED)
(5,6)
t
RC
ADDRESS
t
AA
t
OH
DATA OUT
PREVIOUS DATA VALID
DATA VALID
(9)
READ CYCLE NO. 3 (CE
1
, CE
2
CONTROLLED)
(5,7,10)
CE
t
RC
CE
1
CE
2
t
AC
(10)
DATA VALID
I
CC
V
CC
SUPPLY
CURRENT
I
SB
t
PU
(10)
t
HZ
(8,10)
t
LZ
DATA OUT
(8,10)
HIGH IMPEDANCE
t
PD
(10)
Notes:
9. READ Cycle Time is measured from the last valid address to the first
transitioning address.
10. Transitions caused by a chip enable control have similar delays
irrespective of whether
CE
1
or CE
2
causes them.
95
