P4C1981/P4C1981L, P4C1982/P4C1982L
ULTRA HIGH SPEED 16K x 4
CMOS STATIC RAMS
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25 ns (Commercial)
– 12/15/20/25/35 ns (Industrial)
– 15/20/25/35/45 ns (Military)
Low Power Operation (Commercial/Military)
Output Enable and Dual Chip Enable Functions
5V ± 10% Power Supply
Data Retention with 2.0V Supply, 10 µA Typical
Current (P4C1981L/1982L Military)
Separate Inputs and Outputs
– P4C1981/L Input Data at Outputs during Write
– P4C1982/L Outputs in High Z during Write
Fully TTL Compatible Inputs and Outputs
Standard Pinout (JEDEC Approved)
– 28-Pin 300 mil DIP, SOJ
– 28-Pin 350 x 550 mil LCC
– 28-Pin CERPACK
DESCRIPTION
The P4C1981/L and P4C1982/L are 65,536-bit (16Kx4)
ultra high-speed static RAMs similar to the P4C198, but
with separate data I/O pins. The P4C1981/L feature a
transparent write operation when
OE
is low; the outputs
of the P4C1982/L are in high impedance during the write
cycle. All devices have low power standby modes. The
RAMs operate from a single 5V ± 10% tolerance power
supply. With battery backup, data integrity is maintained
for supply voltages down to 2.0V. Current drain is
typically 10 µA from 2.0V supply.
Access times as fast as 10 nanoseconds are available,
permitting greatly enhanced system operating speeds.
CMOS is used to reduce power consumption. For the
P4C1982L and P4C1981L, power is only 5.5 mW standby
with CMOS input levels.
The P4C1981/L and P4C1982/L are available in 28-pin 300
mil DIP and SOJ, 28-pin 350x550 mil LCC and a 28-pin
CERPACK package providing excellent board level den-
sities.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
DIP (P5, C5, D5-2), SOJ (J5)
CERPACK (F4) SIMILAR
P4C1981/ 1982
LCC (L5)
Document #
SRAM114
REV B
1
Revised August 2006
P4C1981/1981L, P4C1982/1982L
MAXIMUM RATINGS
(1)
Symbol
V
CC
Parameter
Power Supply Pin with
Respect to GND
Terminal Voltage with
Respect to GND
(up to 7.0V)
Operating Temperature
Value
–0.5 to +7
–0.5 to
V
CC
+0.5
–55 to +125
Unit
V
Symbol
T
BIAS
T
STG
P
T
I
OUT
Parameter
Temperature Under
Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
–55 to +125
–65 to +150
1.0
50
Unit
°C
°C
W
mA
V
TERM
T
A
V
°C
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
(2)
Military
Ambient
Temperature
GND
0V
0V
0V
V
CC
5.0V ± 10%
5.0V ± 10%
5.0V ± 10%
CAPACITANCES
(4)
V
CC
= 5.0V, T
A
= 25°C, f = 1.0MHz
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions Typ. Unit
V
IN
= 0V
V
OUT
= 0V
5
7
pF
pF
–55°C to +125°C
–40°C to +85°C
Industrial
0°C to +70°C
Commercial
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage
(2)
Symbol
V
IH
V
IL
V
HC
V
LC
V
CD
V
OL
V
OH
I
LI
I
LO
Parameter
Input High Voltage
Input Low Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
Input Clamp Diode Voltage V = Min., I = –18 mA
CC
IN
Output Low Voltage
I
OL
= +8 mA, V
CC
= Min.
(TTL Load)
Output High Voltage
(TTL Load)
Input Leakage Current
Output Leakage Current
I
OH
= –4 mA, V
CC
= Min.
V
CC
= Max.
V
IN
= GND to V
CC
V
CC
= Max.,
CE
1
,
CE
2
= V
IH
V
OUT
= GND to V
CC
I
SB
Standby Power Supply
V
CC
= Max.,
Ind./Com’l.
Current (TTL Input Levels)
f = Max., Outputs Open
Standby Power Supply
Current
(CMOS Input Levels)
CE
1
,
CE
2
≥
V
HC,
V
CC
= Max.,
f = 0, Outputs Open
V
IN
≤
V
LC
or V
IN
≥
V
HC
n/a = Not Applicable
Test Conditions
P4C1981 / 1982
Min
Max
2.2
–0.5
(3)
–0.5
(3)
0.8
0.2
–1.2
0.4
2.4
Mil.
–10
–5
–10
–5
___
___
___
___
+10
+5
+10
+5
40
35
20
15
P4C1981L / 82L
Unit
Min
Max
V
CC
+0.5
V
CC
+0.5 V
2.2
–0.5
(3)
–0.5
(3)
0.8
0.2
–1.2
0.4
2.4
–5
n/a
–5
n/a
___
___
+5
n/a
+5
n/a
40
n/a
1.0
n/a
mA
mA
V
V
V
V
V
V
µA
µA
V
CC
–0.2 V
CC
+0.5 V
CC
–0.2 V
CC
+0.5
Ind./Com’l.
Mil.
Ind./Com’l.
Mil.
CE
1
,
CE
2
≥
V
IH
,
Mil.
Ind./Com’l.
___
___
I
SB1
Document #
SRAM114
REV B
Page 2 of 13
P4C1981/1981L, P4C1982/1982L
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol
Parameter
Temperature
Range
Commercial
Industrial
Military
CE
1
= V
IL
,
CE
2
= V
IL
,
OE
= V
IH
–10
180
N/A
N/A
–12
170
180
N/A
–15
160
170
170
–20
155
160
160
–25
150
155
155
–35
N/A
150
150
–45
N/A
N/A
145
Unit
mA
mA
mA
I
CC
Dynamic Operating Current*
*V
CC
= 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V.
DATA RETENTION CHARACTERISTICS (P4C1981L/P4C1982L Military Temperature Only)
Symbol
V
DR
I
CCDR
t
CDR
t
R†
*
T
A
= +25°C
§
†
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to
Data Retention Time
Operation Recovery Time
Test Condition
Min
2.0
Typ.*
V
CC
=
2.0V
3.0V
10
15
Max
V
CC
=
2.0V
3.0V
600
900
Unit
V
µA
ns
ns
CE
1
or
CE
2
≥
V
CC
– 0.2V,
V
IN
≥
V
CC
– 0.2V or
V
IN
≤
0.2V
0
t
RC§
t
RC
= Read Cycle Time
This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM ratingconditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
Document #
SRAM114
REV B
Page 3 of 13
P4C1981/1981L, P4C1982/1982L
AC CHARACTERISTICS—READ CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Sym.
t
RC
t
AA
t
AC
t
OH
t
LZ
t
HZ
t
OE
t
OLZ
Parameter
Read Cycle Time
Address Access
Time
Chip Enable
Access Time
Output Hold from
Address Change
Chip Enable to
Output in Low Z
Chip Disable to
Output in High Z
Output Enable
Low to Data Valid
Output Enable to
Output in Low Z
2
2
2
10
-10
12
10
10
2
2
6
6
2
6
0
10
0
-12
-15
15
12
12
2
2
7
7
2
7
0
12
15
9
0
8
8
2
15
15
2
2
20
-20
25
20
20
2
2
10
12
2
9
0
20
-25
35
25
25
2
2
10
15
2
10
0
25
-35
45
35
35
2
2
15
21
2
14
0
25
-45
Unit
ns
Min Max Min
Max Min Max Min Max Min Max Min Max Min Max
45
45
ns
ns
ns
ns
15
27
ns
ns
ns
15
ns
ns
30
ns
t
OHZ
Output Disable to
Output in High Z
t
PU
t
PD
Chip Enable to
Power Up Time
Chip Disable to
Power Down Time
OE
READ CYCLE NO.1 (OE controlled)
(5)
Notes:
5.
WE
is HIGH for READ cycle.
6.
CE
1
,
CE
2
and
OE
are LOW for READ Cycle.
7.
OE
is LOW for the cycle.
8. ADDRESS must be valid prior to or coincident with,
CE
1
, and
CE
2
transition LOW.
9. Transition is measured ±200mV from steady state voltage
prior to change, with loading as specified in Figure 1.
10. Read Cycle Time is measured from the last valid address to
the first transitioning address.
Document #
SRAM114
REV B
Page 4 of 13
P4C1981/1981L, P4C1982/1982L
READ CYCLE NO. 2 (ADDRESS Controlled)
(5,6)
CE
READ CYCLE NO. 3 (CE
1
,
CE
2
Controlled)
(5,7,8)
Note:
11. Transitions caused by a chip enable control have similar delays irrespective of whether
CE
1
or
CE
2
causes them.
Document #
SRAM114
REV B
Page 5 of 13
