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P5020NXE1QMB

IC MPU Q OR IQ 2.0GHZ 1295FCBGA

器件类别:半导体    嵌入式处理器和控制器   

厂商名称:NXP(恩智浦)

厂商官网:https://www.nxp.com

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器件参数
参数名称
属性值
核心处理器
PowerPC e5500
核数/总线宽度
2 코어,64 位
速度
2.0GHz
协处理器/DSP
安全;SEC 4.2
RAM 控制器
DDR3,DDR3L
图形加速
以太网
1 Gbps(5),10 Gbps(1)
SATA
SATA 3Gbps(2)
USB
USB 2.0 + PHY(2)
工作温度
-40°C ~ 105°C(TA)
安全特性
启动安全,密码技术,安全保险丝盒,安全 JTAG,安全存储器,篡改检测
封装/外壳
1295-BBGA,FCBGA
供应商器件封装
1295-FCPBGA(37.5x37.5)
附加接口
DUART,I²C,MMC/SD,SPI
文档预览
TM
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, t
he Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore and Symphony
are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack,
ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a Package, Processor Expert, QorIQ
Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks
of Freescale Semiconductor, Inc. All other product or service names are the property
of their respective owners. © 2011 Freescale Semiconductor, Inc.
Title:
Duplicate edge-triggered interrupt after priority re-arbitration.
Description:
There is an occurrence of duplicate interrupt when an edge-triggered interrupt higher in priority comes closely to any other enabled interrupts. The following
is the sequence of events that leads to the duplicate edge-triggered interrupt::
1. An active interrupt is waiting for acknowledgement
2. An edge-triggered interrupt of higher priority triggers closely to the lower priority interrupt just when it is acknowledged
3. The higher priority edge-triggered interrupt supersedes and fires a new interrupt to the core
4. The core acknowledges the higher priority interrupt without clearing the pending state and finishes the interrupt service routine with EOI
5. A duplicate of the higher priority edge-triggered interrupt is triggered because of the uncleared pending state
Impact:
Enabling any edge-triggered interrupts higher in priority than other enabled interrupts may lead to the duplicate edge-triggered interrupt. This includes
edge-triggered IRQs, global timers and IPI.
Workaround:
Chose one of the following workarounds based on the interrupt type:
• Configure the higher priority interrupts as level-sensitive only
a. In case of IRQs this can be configured in the Vector/Priority Register.
b. It is not an option for global timers or IPI.
• Any enabled edge-triggered interrupts must be no higher in priority than the other enabled interrupts.
Resolution:
No plan to fix
TM
2
Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, the Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, StarCore
and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, Kinetis, MXC, Platform in a
Package, Processor Expert, QorIQ Qonverge, Qorivva, QUICC Engine, SMARTMOS, TurboLink, VortiQa and Xtrinsic are trademarks of Freescale Semiconductor, Inc.
All other product or service names are the property of their respective owners. © 2011 Freescale Semiconductor, Inc.
TM
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