Freescale Semiconductor
Data Sheet: Technical Data
Document Number: P5021
Rev. 1, 05/2014
P5021
P5021 QorIQ
Integrated Processor
Data Sheet
The P5021 QorIQ integrated communication processor
combines two Power Architecture® processor cores with
high-performance data path acceleration logic and network
and peripheral bus interfaces required for networking,
telecom/datacom, wireless infrastructure, and aerospace
applications.
This chip can be used for combined control, data path, and
application layer processing in routers, switches, base station
controllers, and general-purpose embedded computing. Its
high level of integration offers significant performance
benefits compared to multiple discrete devices while also
greatly simplifying board design.
The chip includes the following function and features:
• Two e5500 Power Architecture cores
– Each core has a backside 512 KB L2 cache with ECC
– Three levels of instructions: user, supervisor, and
hypervisor
– Independent boot and reset
– Secure boot capability
• CoreNet fabric supporting coherent and non-coherent
transactions amongst CoreNet endpoints
• Frontside 2 MB CoreNet platform cache with ECC
• CoreNet bridges between the CoreNet fabric the I/Os,
datapath accelerators, and high and low speed peripheral
interfaces
• Two 10-Gigabit Ethernet (XAUI) controllers
• Ten 1-Gigabit Ethernet controllers
– SGMII, 2.5Gb/s SGMII and RGMII interfaces
• Two 64-bit DDR3/3L SDRAM memory controllers with
ECC
• Multicore programmable interrupt controller (PIC)
• Four I
2
C controllers
• Four 2-pin UARTs or two 4-pin UARTs
• Two 4-channel DMA engines
• Enhanced local bus controller (eLBC)
• Three PCI Express 2.0 controllers/ports
•
•
•
•
•
FC-PBGA–1295
37.5 mm
×
37.5 mm
Two serial ATA (SATA) 2.0 controllers
Enhanced secure digital host controller (SD/MMC)
Enhanced serial peripheral interface (eSPI)
Two high-speed USB 2.0 controllers with integrated PHYs
RAID 5 and 6 storage accelerator with support for
end-to-end data protection information
• Data Path Acceleration Architecture (DPAA) incorporating
acceleration for the following functions:
– Frame Manager (FMan) for packet parsing,
classification, and distribution
– Queue Manager (QMan) for scheduling, packet
sequencing and congestion management
– Hardware Buffer Manager (BMan) for buffer allocation
and deallocation
– Encryption/Decryption
• 1295 FC-PBGA package
This figure shows the major functional units within the chip.
Freescale reserves the right to change the detail specifications as may be required
to permit improvements in the design of its products.
© 2013-2014 Freescale Semiconductor, Inc. All rights reserved.
Table of Contents
1
2
Pin assignments and reset states. . . . . . . . . . . . . . . . . . . . . . .3
1.1 1295 FC-PBGA ball layout diagrams . . . . . . . . . . . . . . .3
1.2 Pinout list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
2.1 Overall DC electrical characteristics . . . . . . . . . . . . . . .52
2.2 Power-up sequencing . . . . . . . . . . . . . . . . . . . . . . . . . .58
2.3 Power-down requirements . . . . . . . . . . . . . . . . . . . . . .60
2.4 Power characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .60
2.5 Thermal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
2.6 Input clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
2.7 RESET initialization . . . . . . . . . . . . . . . . . . . . . . . . . . .65
2.8 Power-on ramp rate. . . . . . . . . . . . . . . . . . . . . . . . . . . .66
2.9 DDR3 and DDR3L SDRAM controller. . . . . . . . . . . . . .66
2.10 eSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
2.11 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
2.12 Ethernet: data path three-speed Ethernet (dTSEC),
management interface, IEEE Std 1588. . . . . . . . . . . . .77
2.13 USB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
2.14 Enhanced local bus interface (eLBC) . . . . . . . . . . . . . .87
2.15 Enhanced secure digital host controller (eSDHC) . . . .92
2.16 Multicore programmable interrupt controller (MPIC)
specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
2.17 JTAG controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
3
2.18 I
2
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
2.19 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
2.20 High-speed serial interfaces (HSSI) . . . . . . . . . . . . . 101
Hardware design considerations . . . . . . . . . . . . . . . . . . . . . 129
3.1 System clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
3.2 Supply power default setting . . . . . . . . . . . . . . . . . . . 136
3.3 Power supply design . . . . . . . . . . . . . . . . . . . . . . . . . 137
3.4 Decoupling recommendations . . . . . . . . . . . . . . . . . . 139
3.5 SerDes block power supply decoupling recommendations
140
3.6 Connection recommendations. . . . . . . . . . . . . . . . . . 140
3.7 Recommended thermal model . . . . . . . . . . . . . . . . . 150
3.8 Thermal management information. . . . . . . . . . . . . . . 150
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
4.1 Package parameters for the FC-PBGA . . . . . . . . . . . 151
4.2 Mechanical dimensions of the FC-PBGA . . . . . . . . . 152
Security fuse processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
6.1 Part numbering nomenclature . . . . . . . . . . . . . . . . . . 153
6.2 Orderable part numbers addressed by this document 154
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
4
5
6
7
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
2
Freescale Semiconductor
Pin assignments and reset states
1024 KB
frontside
L3 cache
1024 KB
frontside
L3 cache
64-bit
1600 MT/s DDR-3
memory controller
64-bit
1600 MT/s DDR-3
memory controller
QorIQ P5021
512 KB
backside
L2 cache
eOpenPIC
PreBoot
Loader
Security
Monitor
Internal
BootROM
Power mgmt
SD/MMC
SPI
2x DUART
4x I
2
Cs
2x USB 2.0
+ 2x PHY
Clocks/Reset
GPIO
CCSR
RGMII
RAID5/6
Buffer
Mgr
Test
Port/
SAP
eLBC
Security
5.0
Queue
Mgr
PAMU
PAMU
Power Architecture®
e5500 Core
32 KB
D-cache
32 KB
I-cache
CoreNet™
Coherency Fabric
PAMU
PAMU
PAMU
Peripheral access
management unit (PAMU)
Frame Manager
Parse, classify,
distribute
Buffer
1GE
10GE 1GE
1GE
1GE 1GE
Frame Manager
Parse, classify,
distribute
Buffer
1GE
10GE 1GE
1GE
1GE 1GE
DMA
DMA
Real-time debug
SATA 2.0
PCIe
PCIe
PCIe
Perf CoreNet
monitor trace
18-Lane 5-GHz SerDes
SATA
SerDes
Figure 1. P5021 block diagram
1
1.1
Pin assignments and reset states
1295 FC-PBGA ball layout diagrams
These figures show the FC-PBGA ball map diagrams.
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
3
SATA 2.0
Watchpoint
cross
trigger
Pin assignments and reset states
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
AP
AR
AT
D2_
MDQ
16
D2_
MDQS
2
D2_
MDQ
22
D2_
MDQ
19
RSRV
_F1
RSRV
_G1
D2_
MDQ
31
D2_
MECC
0
D2_
MDQS
8
D2_
MDQS
8
D2_
MBA
2
2
D2_
MDQ
21
GVDD
D2_
MDQS
2
D2_
MDQ
23
GVDD
3
D2_
MDQ
20
D2_
MDQ
17
GND
D2_
MDQ
18
D2_
MDQ
29
GND
D2_
MDM
3
D2_
MDQ
30
GND
D2_
MECC
1
D2_
MECC
6
GND
4
D2_
MDQ
10
D2_
MDQ
11
D2_
MDM
2
GVDD
D2_
MDQ
28
D2_
MDQ
24
GVDD
D2_
MDQ
26
D2_
MECC
4
GVDD
D2_
MECC
7
D2_
MCKE
3
GVDD
D2_
MCKE
2
D2_MA
07
GVDD
5
D2_
MDQS
1
GND
D2_
MDQ
14
D2_
MDQ
15
GND
D2_
MDQ
25
D2_
MDQS
3
GND
D1_
MECC
1
D1_
MDQS
8
GND
D2_
MECC
02
D2_
MECC
3
GND
D2_
MCKE
0
D2_
MCKE
1
GND
D1_
MCK
1
D1_
MCK
0
GND
D1_
MDIC
1
D1_
MDQ
36
GND
D1_
MDQS
4
D1_
MDQ
38
GND
D1_
MDQ
40
D1_
MDQS
5
GND
D2_
MDQ
44
D2_
MDQ
41
GND
D2_
MDQ
43
D2_
MDQ
56
GND
D2_
MDQ
57
6
D2_
MDQS
1
D2_
MDM
1
GVDD
D2_
MDQ
09
D1_
MDQ
22
GVDD
D2_
MDQS
3
D2_
MDQ
27
GVDD
D1_
MDQS
8
D1_MA
15
GVDD
7
D2_
MDQ
08
D2_
MDQ
13
D2_
MDQ
12
GND
D1_
MDQ
23
D1_
MDQ
24
GND
D1_
MDQ
30
D1_
MECC
5
GND
8
D2_
MDQ
03
GVDD
D1_
MDQ
16
D1_
MDQS
2
GVDD
D1_
MDQ
29
D1_
MDQS
3
GVDD
D1_
MECC
4
D1_
MDM
8
9
D2_
MDQ
07
D2_
MDQ
02
GND
D1_
MDQS
2
D1_
MDQ
18
GND
D1_
MDQS
3
D1_
MDQ
31
GND
D1_
MECC
0
D1_
MECC
7
GND
10
D2_
MDQS
0
D2_
MDQ
06
D1_
MDQ
21
GVDD
D1_
MDQ
19
D1_
MDQ
28
GVDD
D1_
MDQ
26
D1_
MDQ
27
11
D2_
MDQS
0
GND
D1_
MDQ
20
D1_
MDM
2
GND
D1_
MDQ
25
D1_
MDM
3
GND
12
D2_
MDQ
01
D2_
MDM
0
GVDD
D1_
MDQ
17
D1_
MDQ
10
GVDD
D1_
MDQ
11
NC_
H12
GVDD
13
D2_
MDQ
04
D2_
MDQ
05
D2_
MDQ
00
GND
D1_
MDQ
14
D1_
MDQ
15
GND
14
D1_
MDQ
03
GVDD
D1_
MDQ
02
D1_
MDM
1
GVDD
D1_
MDQS
1
D1_
MDQS
1
GVDD
15
D1_
MDQ
06
D1_
MDQ
07
GND
D1_
MDQ
08
D1_
MDQ
13
GND
D1_
MDQ
09
NC_
H15
LA
30
LWE
3
VDD_PL
16
D1_
MDM
0
D1_
MDQS
0
D1_
MDQS
0
GVDD
17
D1_
MDQ
00
D1_
MDQ
05
D1_
MDQ
04
D1_
MDQ
01
GND
18
GND
19
AVDD_
DDR
MVREF
NC_
C19
LCS
00
GND
20
AVDD_
CC1
GND
21
RSRV
_A21
TEMP_
CATH-
ODE
22
GND
23
LALE
LCS
5
LCLK
1
LAD
09
LAD
08
GND
24
LWE
1
BVDD
25
RSRV
_A25
LGPL
0
LGPL
4
LGPL
2
LGPL
1
LAD
04
LA
17
LAD
03
LA
16
26
GND
27
NC_
A27
28
SGND
29
SD_RX
01
SD_RX
01
SGND
30
SVDD
31
SD_RX
03
SD_RX
03
SVDD
32
SGND
33
AVDD_
SRDS1
AGND_
SRDS1
SGND
34
SVDD
35
SD_
REF_
CLK1
SD_
REF_
CLK1
SVDD
36
SGND
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
AL
AM
AN
AP
AR
AT
GND
GND
NC_
B26
NC_
C26
LAD
27
LGPL
5
BVDD
SD_IMP_ SVDD
CAL_RX
NC_
C27
NC_
D27
NC_
E27
GND
SD_RX
00
SD_RX
00
XGND
SGND
SVDD
SGND
SVDD
GVDD
NC_
C20
LCS
1
LCS
2
BVDD
TEMP_
LBCTL
ANODE
LCS
3
LA
21
LA
22
GND
LCS
4
BVDD
LCLK
0
LWE
0
BVDD
SD_RX
02
SD_RX
02
XGND
RSRV
_C32
RSRV
_D32
XVDD
SVDD
SD_RX
04
SD_RX
04
SVDD
NC_
D18
LA
28
LA
29
LAD
31
BVDD
SVDD
SGND
XGND
SD_TX
04
SD_TX
04
SVDD
SGND
NC_
E16
D1_
MDQ
12
GVDD
SD_TX
01
SD_TX
01
XGND
SD_TX
03
SD_TX
03
XGND
XVDD
SGND
RSRV
_F2
RSRV
_G2
GVDD
D2_
MECC
5
D2_
MDM
8
GVDD
LA
31
GND
LAD
12
LA
28
LA
29
LA
30
GND
LA
19
LAD
11
LA
20
LAD
10
BVDD
LCS
6
LAD
06
LAD
05
LDP
0
BVDD
XVDD
XVDD
XGND
SD_TX
05
SD_TX
05
XVDD
SD_RX SD_RX
05
05
SVDD
SGND
LA
25
BVDD
LAD
07
LA
18
GND
LCS
7
LGPL
3
LAD
02
NC_
G27
NC_
H27
GND
SD_TX
00
SD_TX
00
XVDD
SD_TX
02
SD_TX
02
XVDD
XVDD
SGND
NC_
H13
NC_
J13
NC_
K13
VDD_PL
LDP
3
LWE
2
LDP
02
LAD
15
LA
23
GND
XGND
XVDD
XGND
XGND
SD_RX SD_RX
06
06
SGND
SVDD
SEE DETAIL A
GVDD
NC_
K11
GVDD
D1_
MBA
2
D1_
VDD_PL
MECC
2
D1_
MECC
3
GND
NC_
J11
NC_
J14
NC_
K14
GND
LAD
13
LAD
14
GND
LA
26
LA
27
GND
XGND
XGND
XVDD
NC_
K12
SENSE- SENSE-
VDD_CA GND_CA
GND
VDD_PL
LA
24
VDD_PL
LDP
1
VDD_PL
GND
SEE DETAIL B
LAD
00
SENSE-
GND_PL
2
SENSE-
VDD_PL
2
GND
XGND
XGND
LAD
01
VDD_PL
RSRV
_L28
RSRV
_M28
RSRV
_N28
RSRV
_P28
XGND
XVDD
SD_TX
06
SGND
SD_TX
06
SVDD
XVDD
SD_TX
07
XVDD
SD_TX
07
XGND
SD_RX SD_RX
07
07
SVDD
SGND
D1_
MECC
6
D1_MA
14
GND
VDD_PL
GND
GND
VDD_PL
XVDD
SD_RX SD_RX
08
08
SVDD
SGND
D2_MA
15
VDD_PL
GND
VDD_PL
GND
VDD_CA
GND
VDD_CA
GND
VDD_CA
GND
VDD_PL
GND
VDD_PL
GND
XGND
SD_TX
08
XVDD
SD_TX
08
XGND
SD_RX SD_RX
09
09
SGND
SVDD
D2_
D2_MA
D2_MA
MAPAR_
12
14
ERR
D2_MA
09
GVDD
D2_MA
11
GND
D1_
D1_
D1_MA GND
MAPAR_ MCKE
12
3
ERR
D1_
D1_MA D1_MA GVDD MCKE
09
11
2
GVDD
D1_
MDIC
0
D1_MA D1_MA
08
07
GND
GND
GVDD VDD_PL
D1_
MCKE
0
GND
VDD_PL
GND
VDD_CA
GND
VDD_CA
GND
VDD_CA
GND
VDD_CA
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL
XGND
XGND
SD_TX
09
XVDD
SD_TX
09
XGND
GND
VDD_PL
GND
VDD_CA
GND
VDD_CA
GND
VDD_CA
GND
VDD_CA
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL
GND
XGND
XVDD
SD_TX
10
XVDD
SD_TX
10
XGND
SD_RX SD_RX
10
10
SVDD
SGND
D2_MA D2_MA
06
08
D1_
VDD_PL
MCKE
1
GVDD
GND
GND
VDD_PL
GND
VDD_CA
GND
VDD_CA
GND
VDD_CA
GND
VDD_CA
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL AVDD_
SRDS4
GND
AGND_
SRDS4
SD_
REF_
CLK4
SD_
REF_
CLK4
VDD_PL
XVDD
XGND
SGND
SVDD
D2_MA D2_MA D2_MA
03
04
05
D2_MA
01
D2_
MCK
2
D2_
MCK
3
GVDD
D2_
MCK
2
D2_
MCK
3
GND
D2_
MCK
1
D2_
MCK
0
GND
D2_
MBA
0
D2_
MCS
2
D2_
MCAS
GND
D2_
MODT
3
D2_
MDQ
37
GND
D2_
MDQS
4
D2_
MDQ
34
GND
D2_
MDM
5
D2_
MDQS
5
GND
D2_
MDQ
49
D2_
MDQ
54
D2_
MDQ
55
D1_MA D1_MA
05
06
GVDD
D1_
MCK
2
D1_
MCK
3
VDD_PL
GND
VDD_PL
GND
VDD_CA
GND
VDD_CA
GND
VDD_CA
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL
XVDD
SD_TX
11
XVDD
SD_TX
11
XGND
XVDD
SD_RX
11
SVDD
SD_
REF_
CLK2
SGND
SD_RX
11
SGND
SD_
REF_
CLK2
SVDD
SGND
AGND_
SRDS2
AVDD_
SRDS2
SGND
D2_MA
02
D2_
MCK
1
D2_
MCK
0
D2_MA
00
D2_
MDIC
0
GVDD
D1_MA D1_MA
01
02
D1_
MCK
1
D1_
MCK
0
D2_
MDIC
1
GVDD
D1_MA D1_MA VDD_PL
03
04
D1_
MCK
2
D1_
MCK
3
D1_MA
00
GND
D1_
MCS
2
D1_
MCS
0
GND
D1_
MCS
1
D1_
MCS
3
GND
D1_
MDQ
41
D1_
MDQ
42
GND
D1_
MDQ
48
D1_
MDQS
6
GND
D1_
MDQ
60
D1_
MDQ
61
D1_
MDQ
56
GND
GND
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL
XGND
RSRV
_U32
XVDD
RSRV
_U35
SVDD
VDD_PL
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL
GND
NC_
W27
GND
XGND
XVDD
XGND
GND
GVDD VDD_PL
D1_
MBA
1
GND
VDD_PL
GND
GND
GND
GND
GND
GND
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL
GND
XVDD
XGND
SD_TX
12
XVDD
SD_TX
12
XGND
SD_RX SD_RX
12
12
SGND
D2_
GVDD
MAPAR_
OUT
D2_
D2_MA
MBA
10
1
D2_
MRAS
D2_
MCS
0
D2_
MODT
2
D2_
MCS
1
D2_
MODT
1
D2_
MDM
4
D2_
MDQ
38
D2_
MDQ
35
RSRV
_AK1
RSRV
_AL1
D2_
MDQ
52
D2_
MDQ
48
D2_
MDQS
6
D2_
MDQS
6
D2_
MDQ
50
D2_
MWE
GVDD
D2_
MODT
0
D2_
MCS
3
GVDD
D2_
MDQ
33
D2_
MDQS
4
GVDD
D1_
GVDD
MAPAR_
OUT
D1_
GVDD D1_MA
MBA
10
0
D1_
MDQ
37
D1_
MDQ
33
GVDD
D1_
MDQ
39
D1_
MDQ
34
GVDD
D1_
MDQS
5
D1_
MDQ
46
GVDD
D2_
MDQ
40
D2_
MDQ
46
GVDD
D2_
MDM
7
D2_
MDQS
7
D2_
MDQS
7
GND
D1_
MDQ
32
D1_
MDM
4
GND
D1_
MDQ
35
D1_
MDQ
45
GND
D1_
MWE
GVDD
D1_
MODT
2
D1_MA
13
GVDD
D1_
MDQ
44
GND
VDD_PL
GND
VDD_PL
GND
GND
GND
GND
GND
GND
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL
XGND
SD_TX
13
SD_TX
13
XGND
SD_RX
13
SVDD
SD_RX
13
SGND
SVDD
D1_ VDD_PL
MRAS
GVDD
GND
GND
VDD_PL
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL SD1_IMP_ XVDD
CAL_TX
GND
SD_TX
18
VDD_
LL
VDD_
LP
SD_TX
18
S1VDD
SD_TX
14
XVDD
SD_
REF_
CLK3
XGND
SD_TX
14
XGND
SD_
REF_
CLK3
XVDD
SD_RX SD_RX
14
14
SVDD
SGND
VDD_PL
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL
XVDD
SD_TX
15
XVDD
SD_TX
15
XGND
D2_MA
13
D1_
MDQS
4
GVDD
D2_
MDQ
36
D2_
MDQ
32
GVDD
D2_
MDQ
39
D2_
MDQ
45
GVDD
D2_
MDQS
5
D2_
MDQ
42
GVDD
D2_
MDQ
60
D2_
MDQ
61
D1_ VDD_PL
MCAS
D1_
MODT
0
GND
GND
VDD_PL
GND
GND
GND
GND
GND
GND
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL
XGND
SD_RX SD_RX
15
15
SGND
SVDD
VDD_PL
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL
GND
SD_RX
18
XGND
RSRV
_AD33
SVDD
RSRV
_AD34
SGND
GVDD VDD_PL
D1_
MODT
3
D1_
MODT
1
GVDD
D1_
MDQ
43
GVDD
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL
GND
GND
LP_TMP SD_RX
_DETECT 18
XVDD
SD_TX
16
SD_TX
16
XGND
AVDD_ AGND_
SRDS3 SRDS3
SVDD
SGND
SENSE- SENSE-
VDD_PL GND_PL
1
1
RSRV
_AG11
RSRV
_AG12
RSRV
_AH12
OVDD
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL
GND
SD1_IMP SD_RX SD_RX
19
CAL_RX
19
SD_TX X1VDD
19
USB2_
VDD_
1P0
USB2_
TMS
AGND
S1V
DD
SGND SD_IMP_ XVDD
CAL_TX
RSRV
_AG29
XGND
SD_TX
17
SD_RX
16
SGND
SD_RX
16
SVDD
SEE DETAIL C
D1_
MDM
5
RSRV
_AH11
GND
GVDD
D1_
MDQ
52
D1_
MDQ
49
GVDD
D1_
MDQ
55
D2_
MDQ
58
GVDD
D2_
MDQ
59
IRQ
09
D1_
MDM
6
GND
D1_
MDQ
51
TEST_
SEL2
GND
D1_
MDQS
7
IRQ
02
IRQ
11
IRQ
08
GND
IIC4_
SCL
IRQ
10
OVDD
NC_
AG15
IIC1_
SCL
IRQ
03
GND
GND
IRQ
06
IRQ
04
EVT
0
EVT
1
SCAN_
MODE
GND
IRQ
01
IRQ
00
EVT
3
OVDD
DMA2_ GPIO
OVDD
DACK
07
0
IO_
MSRCID VSEL MSRCID GPIO
0
04
2
4
GND
OVDD MSRCID DMA2_
DREQ
1
0
IO_
CLK_
GND
VSEL
OUT
2
IO_
VSEL
0
DMA1_
DACK
0
OVDD
GPIO
05
GPIO
06
GPIO
00
GND
DMA1_
DDONE
0
DMA1_
DREQ
0
ASLEEP
TEST_
SEL
PD
17
GND
PD
13
CVDD
SD_TX
19
USB1_
VDD_
1P0
SD_TX
17
XVDD
SD_RX SD_RX
17
17
SGND
SVDD
UART2_ USB1_
AGND
CTS
OVDD
USB1_
AGND
D1_
MDQ
47
D1_
MDQ
53
GND
D2_
MDQ
47
D1_
MDQ
54
GND
D2_
MDQ
62
D2_
MDQ
63
IRQ
05
IIC3_
SCL
GND
UART2_
SOUT
GPIO
01
SEE DETAIL D
USB1_
VDD_
3P3
USB1_
VBUS_
CLMP
USB2_
VDD_
3P3
USB2_ SPI_CS
VDD_
1
3P3
CVDD
USB2_ USB2_
GND
VBUS_
UID
CLMP
USB2_
USB1_ USB1_
USB1_
VDD_1P8 VDD_1P8
AGND
AGND
_DECAP _DECAP
USB1_
IBIAS_
REXT
USB2_
AGND
USB2_
UDM
USB2_
IBIAS_
REXT
USB2_
AGND
USB2_
UDP
SPI_
CLK
SPI_
MISO
EC2_ SD_PLL4 XGND
RX_ER _TPD
EMI2_ EC_XTRNL
MDIO _TX_STMP
2
SGND
GND
GND
TSEC_
TSEC_
LV
EMI1_
1588_PULSE DD 1588_ALARM
MDC
_OUT1
_OUT2
RSRV
_AK2
RSRV
_AL2
GVDD
D2_
MDQ
53
D2_
MDM
6
GVDD
D2_
MDQ
51
IRQ_
OUT
IIC2_
SDA
IIC3_
SDA
IIC1_
SDA
VID_
VDD_CA
_CB1
GVDD
UART2_ USB1_
UID
RTS
USB1_
VDD_
3P3
USB_
CLKIN
RTC
PD
14
OVDD
PD
15
GVDD
D1_
MDQS
6
D1_
MDQ
50
GVDD
D1_
MDQ
57
D1_
MDM
7
IIC4_
SDA
IIC2_
SCL
GND
UART1_ SHDC_
SOUT
CLK
UART1_ SDHC_
DAT
RTS
2
OVDD UART2_
SIN
UART1_
CTS
TCK
GND
GND
VID_
VDD_CA
_CB3
GVDD
D1_
MDQ
63
D1_
MDQ
62
D1_
MDQS
7
IRQ
07
VID_
VDD_CA
_CB2
GND
D1_
MDQ
59
D1_
MDQ
58
EVT
4
EVT
2
IO_
CKSTP_
VSEL
OUT
3
OVDD
TMP_
DETECT
GND
GPIO
02
GPIO
03
DMA2_
DDONE
0
TMS
USB1_
AGND
USB2_
AGND
USB2_
AGND
USB1_
AGND
USB1_
AGND
TSEC_
EC1_ TSEC_
EMI2_ EC_XTRNL EC_XTRNL LVDD
GTX_ 1588_ALARM1588_TRIG
MDC _RX_STMP _RX_STMP
_IN2
CLK125 _OUT2
2
1
TSEC_
EC2_
TSEC_ TSEC_
LV
EMI1_
GND
GND
1588_PULSE DD
GTX_
1588_CLK 1588_TRIG
MDIO
_OUT01
CLK125
_IN1
_IN
EC1_
LVDD
EC1_
EC1_
USB2_ SPI_CS TSEC_ EC_XTRNL GND
RXD
_TX_STMP
RX_CLK
RX_DV
AGND
3 1588_CLK_
03
1
OUT
GND
PD
12
LVDD
PD
06
PD
07
GND
LVDD
EC1_
RXD
2
GND
TDI
USB2_ SPI_CS
AGND
0
USB2_
AGND
CVDD
EC1_
RXD
1
EC1_
GTX_
CLK
LVDD
EC1_
TXD
0
EC1_
RXD
0
EC1_
TXD
3
EC1_
TX_EN
GND
TDO
IO_
OVDD
PORESET VSEL
1
GND
HRESET
GND
PD
02
PD
03
PD
04
PD
05
PD
10
PD
11
MDVAL
TRST
UART1_
SIN
SYSCLK
USB1_ USB1_
AGND AGND
USB1_
UDM
USB2_ SPI_CS
AGND
2
SPI_
MOSI
PD
09
PD
01
EC1_
TXD
1
EC1_
TXD
2
OVDD RESET_
VID_
AVDD_ AVDD_ AVDD_
POVDD
VDD_CA
FM
CC2
PLAT
REQ
_CB0
USB1_ USB2_
AGND
UDP
PD
08
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Signal Groups
OVDD
I/O Supply Voltage
I/O Supply Voltage
DDR DRAM I/O Supply
SPI Voltage Supply
Local Bus I/O Supply
SVDD
SerDes Core Power Supply
SerDes Transcvr Pad Supply
Platform Supply Voltage
Core Group A Supply Voltage
AVDD_
SRDS1
AVDD_
SRDS2
AVDD_
PLAT
AVDD_
CC
SENSE-
VDD_PL
SerDes 1 PLL Supply Voltage
SerDes 2 PLL Supply Voltage
Platform PLL Supply Voltage
Core PLL Supply Voltage
Platform Voltage Sense
SENSE-
VDD
SENSE-
VDD_CB
Core Group A Voltage Sense
Core Group B Voltage Sense
Reserved
Fuse Programming Override Supply
LVDD
XVDD
GVDD
VDD_
PL
VDD_
CA
RSRV
CVDD
POVDD
BVDD
Figure 2. 1295 BGA ball map diagram (top view)
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
4
Freescale Semiconductor
Pin assignments and reset states
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
D2_
MDQ
16
D2_
MDQS
2
D2_
MDQ
22
D2_
MDQ
19
RSRV
_F1
RSRV
_G1
D2_
MDQ
31
D2_
MECC
0
D2_
MDQS
8
D2_
MDQS
8
D2_
MBA
2
2
D2_
MDQ
21
GVDD
D2_
MDQS
2
D2_
MDQ
23
GVDD
3
D2_
MDQ
20
D2_
MDQ
17
GND
D2_
MDQ
18
D2_
MDQ
29
GND
D2_
MDM
3
D2_
MDQ
30
GND
D2_
MECC
1
D2_
MECC
6
GND
4
D2_
MDQ
10
D2_
MDQ
11
D2_
MDM
2
GVDD
D2_
MDQ
28
D2_
MDQ
24
GVDD
D2_
MDQ
26
D2_
MECC
4
GVDD
D2_
MECC
7
D2_
MCKE
3
GVDD
D2_
MCKE
2
D2_MA
07
GVDD
5
D2_
MDQS
1
GND
D2_
MDQ
14
D2_
MDQ
15
GND
D2_
MDQ
25
D2_
MDQS
3
GND
D1_
MECC
1
D1_
MDQS
8
GND
D2_
MECC
2
D2_
MECC
3
GND
D2_
MCKE
0
D2_
MCKE
1
GND
D1_
MCK
1
6
D2_
MDQS
1
D2_
MDM
1
GVDD
D2_
MDQ
09
D1_
MDQ
22
GVDD
D2_
MDQS
3
D2_
MDQ
27
GVDD
D1_
MDQS
8
D1_MA
15
GVDD
7
D2_
MDQ
08
D2_
MDQ
13
D2_
MDQ
12
GND
D1_
MDQ
23
D1_
MDQ
24
GND
D1_
MDQ
30
D1_
MECC
5
GND
D1_
MECC
6
D1_MA
14
GND
8
D2_
MDQ
03
GVDD
D1_
MDQ
16
D1_
MDQS
2
GVDD
D1_
MDQ
29
D1_
MDQS
3
GVDD
D1_
MECC
4
D1_
MDM
8
GVDD
D1_
MBA
2
9
D2_
MDQ
07
D2_
MDQ
02
GND
D1_
MDQS
2
D1_
MDQ
18
GND
D1_
MDQS
3
D1_
MDQ
31
GND
D1_
MECC
0
D1_
MECC
7
GND
10
D2_
MDQS
0
D2_
MDQ
06
D1_
MDQ
21
GVDD
D1_
MDQ
19
D1_
MDQ
28
GVDD
D1_
MDQ
26
D1_
MDQ
27
GVDD
11
D2_
MDQS
0
GND
D1_
MDQ
20
D1_
MDM
2
GND
D1_
MDQ
25
D1_
MDM
3
GND
12
D2_
MDQ
01
D2_
MDM
0
GVDD
D1_
MDQ
17
D1_
MDQ
10
GVDD
D1_
MDQ
11
NC_
H12
GVDD
13
D2_
MDQ
04
D2_
MDQ
05
D2_
MDQ
00
GND
D1_
MDQ
14
D1_
MDQ
15
GND
14
D1_
MDQ
03
GVDD
D1_
MDQ
02
D1_
MDM
1
GVDD
D1_
MDQS
1
D1_
MDQS
1
GVDD
15
D1_
MDQ
06
D1_
MDQ
07
GND
D1_
MDQ
08
D1_
MDQ
13
GND
D1_
MDQ
09
NC_
H15
LAD
30
LWE
3
VDD_PL
16
D1_
MDM
0
D1_
MDQS
0
D1_
MDQS
0
GVDD
17
D1_
MDQ
00
D1_
MDQ
05
D1_
MDQ
04
D1_
MDQ
01
GND
18
GND
GND
GVDD
NC_
D18
LAD
28
LAD
29
LA
31
BVDD
NC_
E16
D1_
MDQ
12
GVDD
RSRV
_F2
RSRV
_G2
GVDD
D2_
MECC
5
D2_
MDM
8
GVDD
LAD
31
GND
NC_
H13
NC_
J13
NC_
K13
VDD_PL
LDP
3
LWE
2
LDP
2
LAD
15
NC_
J11
NC_
K11
NC_
J14
NC_
K14
GND
LAD
13
LAD
14
GND
NC_
K12
GND
SENSE- SENSE-
VDD_CA GND_CA
GND
VDD_PL
D1_
VDD_PL
MECC
2
D1_
MECC
3
GND
D2_MA
15
VDD_PL
GND
VDD_PL
GND
VDD_CA
GND
VDD_CA
D2_
D2_MA
D2_MA
MAPAR_
12
14
ERR
D2_MA
09
GVDD
D2_MA
11
GND
D1_
D1_
MAPAR_ MCKE
3
ERR
D1_
D1_MA D1_MA GVDD MCKE
09
11
2
D1_MA
12
GVDD
D1_
MDIC
0
D1_MA D1_MA
07
08
GND
GND
GVDD VDD_PL
D1_
MCKE
0
GND
VDD_PL
GND
VDD_CA
GND
VDD_CA
GND
GND
VDD_PL
GND
VDD_CA
GND
VDD_CA
GND
VDD_CA
D2_MA D2_MA
06
08
D1_
VDD_PL
MCKE
1
GVDD
GND
GND
VDD_PL
GND
VDD_CA
GND
VDD_CA
GND
D2_MA D2_MA D2_MA
03
04
05
D2_MA
01
D2_
MCK
2
GVDD
D2_
MCK
2
GND
D2_
MCK
1
D1_MA D1_MA
06
05
GVDD
D1_
MCK
2
VDD_PL
GND
VDD_PL
GND
VDD_CA
GND
VDD_CA
D2_MA
02
D2_
MCK
1
D1_MA D1_MA
01
02
D1_
MCK
1
GVDD
D1_MA D1_MA VDD_PL
03
04
D1_
MCK
2
GND
GND
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL
GND
VDD_PL
DETAIL A
Figure 3. 1295 BGA ball map diagram (detail view A)
P5021 QorIQ Integrated Processor Data Sheet, Rev. 1
Freescale Semiconductor
5
