P5xC012/020/024/037/052 family
Secure contact PKI smart card controller
Rev. 3.1 — 5 January 2010
138531
Product short data sheet
PUBLIC
1. General description
1.1 SmartMX family approach
The new CMOS14 SmartMX family members feature a modular set of devices with:
•
•
•
•
•
•
•
•
•
12 KB to 52 KB EEPROM
160 KB to 264 KB user ROM
3584 B or 6144 B RAM
High-performance secured Public Key Infrastructure (PKI) coprocessor (RSA, ECC)
Secured dual/triple-DES coprocessor
Memory Management Unit (MMU)
ISO/IEC 7816 contact interface
5-metal-layer 0.14
μm
CMOS technology
EEPROM with minimum 500 000 cycles endurance and minimum 25 years retention
time
•
Broad spectrum of delivery types
•
Optional certified crypto library modules for RSA and ECC
1.2 SmartMX family properties
The long-term approved SmartMX family features a significantly enhanced secure smart
card IC architecture. Extended instructions for Java and C code, linear addressing, high
speed at low power and a universal memory management unit are among many other
improvements added to the classic 80C51 core architecture. The technology transfer step
from 5-metal-layer 0.18
μm
to 5-metal-layer 0.14
μm
CMOS technology offers now even
more advantages in terms of security features, memory resources, crypto coprocessor
calculation speed for RSA and ECC as well as availability of secure hardware support for
2/3-key Data Encryption Standard (DES) operations.
The contact interface availability enables the easy implementation of native or open
platform and multi-application operating systems in market segments such as banking,
E-passport, ID card, secure access, Java card as well as Trusted Platform Modules (TPM)
within extremely tiny SMD packages.
NXP Semiconductors
P5xC012/020/024/037/052 family
Secure contact PKI smart card controller
1.3 Naming conventions
Table 1.
x
Naming conventions
Type of category:
C = PKI controller + Triple-DES coprocessor
S = Triple-DES coprocessor
y
zzz
Interface options:
C = contact interface - ISO/IEC 7816
Amount of non-volatile memory in KB, increasing count for further product options
P5xyzzz SmartMX platform
1.4 Cryptographic hardware coprocessors
1.4.1 FameXE coprocessor
The approved and modular FameXE architecture supports the trend of increasing RSA
keys with faster execution speeds as well as Elliptic Curve Cryptography (ECC) based on
GF(p) or GF(2
n
) at best performance. FameXE supports RSA with an operand length of
up to 8-kbit (up to 4-kbit with intermediate storage in RAM only).
The FameXE PKI coprocessor supports 192-bit ECC key length that offers the same level
of security as 2048-bit RSA. An ECC GF(2
n
) based signature, using a 163-bit key can be
executed in less than 30 ms providing a security level comparable to 1024-bit RSA. The
operand size for ECC, supported by FameXE, is only limited by the 2.5 KB size of the
FXRAM. FameXE is easy to use and the flexible interface provides programmers with the
freedom to implement their own cryptology solutions. A secured and EAL5+ CC certified
crypto library providing a large range of required functions will be available for all devices
in order to support customers in implementing public key-based solutions.
1.4.2 Triple-DES coprocessor
The DES for widely used symmetric encryption is supported by a dedicated, high
performance, highly attack resistant hardware coprocessor. Single DES and triple-DES,
based on two or three DES keys, can be executed within less than 40
μs.
Relevant
standards (ISO/IEC, ANSI, FIPS) and Message Authentication Code (MAC) are fully
supported. A secured crypto library element for DES is available.
1.5 SmartMX interfaces
1.5.1 SmartMX contact interface
Operating in accordance with ISO/IEC 7816, the SmartMX contact interface is supported
by a built-in Universal Asynchronous Receiver/Transmitter (UART), which enables data
rates of up to 1 Mbit/s allowing for the automatic generation of all typical baud rates and
supports transmission protocols T=0 and T=1. An additional IO is available for proprietary
use.
P5XC012_02X_037_052_FAM_SDS_2
© NXP B.V. 2010. All rights reserved.
Product short data sheet
PUBLIC
Rev. 3.1 — 5 January 2010
138531
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NXP Semiconductors
P5xC012/020/024/037/052 family
Secure contact PKI smart card controller
1.6 Security features
SmartMX incorporates a big range of both inherent and OS controlled security features as
counter measure against all types of attacks. NXP Semiconductors has used the deep
knowledge of chip security, combined with the used handshaking circuit technology, the
very dense 5-metal-layer 0.14
μm
technology, glue logic and active shielding methodology
for optimum results in CC EAL5+, EMVCo and other third party certifications and
approvals.
SmartMX Memory Management Unit (MMU), designed to define various memory
segments and assign security attributes accordingly, supports a strong firewall concept
that keeps different applications separate from each other. Only the System mode has full
access privileges to all memory space and on-chip peripherals, while in User mode the
privileges are limited. User mode restrictions are configurable by software running in
System mode.
The SmartMX security features are acknowledged by most of the NXP Semiconductors
customers for their outstanding properties. The counter measures against light attacks are
regarded as “best-in-class”.
1.7 Security evaluation and certificates
The reached target of the certification is CC EAL5+. Also third party approvals such as
EMVCo (VISA, CAST), ZKA and others, depending on the application requirements, are
available.
NXP Semiconductors continues to drive forward third party security evaluations to provide
its customers with the relevant information and documentation needed to execute
subsequent composite evaluations of implemented applications.
1.8 Security licensing
Above and beyond the various intellectual properties regarding attack resistance of the
SmartMX family owned by NXP Semiconductors, NXP Semiconductors has obtained a
patent license for SPA and DPA countermeasures from Cryptography Research, Inc.
(CRI). This license covers both hardware and software countermeasures. It is of special
importance for the customers that countermeasures within the operation system are
covered under this license agreement with CRI. Further details can be obtained on
request.
1.9 Optional crypto library
NXP Semiconductors will offer for all family types an optional crypto library:
•
Various algorithms
–
DES and Triple-DES encryption and decryption using the DES coprocessor
–
RSA encryption and decryption, signature generation and verification for
straightforward and CRT keys up to 5024 bits
–
RSA key generation
–
ECC over GF(p) signature generation and verification (ECDSA) and
Diffie-Hellmann key exchange for keys up to 544 bits
–
ECC over GF(p) key generation
P5XC012_02X_037_052_FAM_SDS_2
© NXP B.V. 2010. All rights reserved.
Product short data sheet
PUBLIC
Rev. 3.1 — 5 January 2010
138531
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NXP Semiconductors
P5xC012/020/024/037/052 family
Secure contact PKI smart card controller
–
ECC over GF(2
n
) signature generation and verification (ECDSA) and
Diffie-Hellmann key exchange for keys up to 571 bits
–
ECC over GF(2
n
) key generation
–
SHA-1, SHA-224 and SHA-256 hash algorithm
–
Pseudo-Random Number Generator (PRNG)
•
Easy to use API for all algorithms
•
Latest built-in security features to avoid power (SPA/DPA), timing and fault attacks
(DFA)
•
Common criteria EAL5+ certification available (except ECC over GF(2
n
)) according to
BSI-PP-0002 protection profile
2. Features
2.1 Standard family features
EEPROM: choice of 12 KB, 20 KB, 24 KB, 36 KB or 52 KB
Data retention time: 25 years minimum
Endurance: 500 000 cycles minimum
ROM: 160 KB, 200 KB or 264 KB (depending on EEPROM size)
RAM for P5CC012/020/024/037/052: 6144 B
256 B IRAM + 3.25 KB Standard RAM usable for CPU
2560 B FXRAM usable for FameXE
RAM for P5SC020: 3584 B
256 B IRAM + 3.25 KB Standard RAM usable for CPU
Dedicated Secure_MX51 Smart Card CPU (Memory eXtended/enhanced 80C51)
5-metal layer 0.14
μm
CMOS technology
Operating in Contact mode
Featuring a 24-bit universal memory space, 24-bit program counter
Combined universal program and data linear address range up to 16 MB
Additional instructions to improve
- pointer operations
- performance
- code density of both C and Java source code
ISO/IEC 7816 contact interface
PKI coprocessor FameXE
High-speed Triple-DES coprocessor (64-bit parallel processing DES engine)
Two or three keys loadable
Triple-DES calculation time < 40
μs
Memory Management Unit (MMU)
Low power and low voltage design using NXP Semiconductors handshaking
technology
Multiple source vectorized interrupt system with four priority levels
Watch exception provides software debugging facility
Multiple source RESET system
Two 16-bit timers
P5XC012_02X_037_052_FAM_SDS_2
© NXP B.V. 2010. All rights reserved.
Product short data sheet
PUBLIC
Rev. 3.1 — 5 January 2010
138531
4 of 16
NXP Semiconductors
P5xC012/020/024/037/052 family
Secure contact PKI smart card controller
High reliable EEPROM for both data storage and program execution
Bytewise EEPROM programming and read access
Versatile EEPROM programming of 1 B to 64 B at a time
Typical EEPROM page erasing time: 1.7 ms
Typical EEPROM page programming time: 1.0 ms
Power-saving IDLE mode
Wake-up from IDLE mode by RESET or any activated interrupt
Power-saving SLEEP or CLOCKSTOP mode
Wake-up from SLEEP or CLOCKSTOP mode by RESET or external interrupt
Contact configuration and serial interface according to ISO/IEC 7816: GND, VCC,
CLK, RST, I/O
One additional IO port IO3 for proprietary use
ISO/IEC 7816 UART supporting standard protocols T=0 and T = 1 as well as high
speed personalization up to 1 Mbit/s
Support of major Public Key Cryptography (PKC) systems like RSA, Elgamel, DSS,
Diffie-Hellman, Guillou-Quisquater, Fiat-Shamir and Elliptic Curves
8192 bits maximum key length for RSA with randomly chosen modulus
4096 bits maximum key length for calculation within RAM
32-bit interface
Boolean operations for acceleration of standard, symmetric cipher algorithms
Externally or internally generated configurable CPU clock
1 MHz to 10 MHz operating external clock frequency range
Internal clocking independent of externally applied frequency
High speed 16-bit CRC engine according to ITU-T polynom definition
Low power Random Number Generator (RNG) in hardware, AIS-31 compliant
1.62 V to 5.5 V operating voltage range for Class C, B and A
Optional extended Class B operation mode (2.2 V to 3.3 V targeted for battery
supplied applications)
−25 °C
to +85
°C
ambient temperature
Broad spectrum of delivery types
Wafers
Modules
Tiny SMD packages
2.2 Security features
Enhanced security sensors
Low/high clock frequency sensor
Low/high temperature sensor
Low/high supply voltage sensor
Single Fault Injection (SFI) attack detection
Light sensors (including integrated memory light sensor functionality)
Electronic fuses for safeguarded mode control
Active Shielding
Unique ID for each die
Clock input filter for protection against spikes
P5XC012_02X_037_052_FAM_SDS_2
© NXP B.V. 2010. All rights reserved.
Product short data sheet
PUBLIC
Rev. 3.1 — 5 January 2010
138531
5 of 16