INTEGRATED CIRCUITS
80C552/83C552
Single-chip 8-bit microcontroller with
10-bit A/D, capture/compare timer,
high-speed outputs, PWM
Product data
Supersedes data of 1998 Aug 13
2002 Sep 03
Philips
Semiconductors
Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
80C552/83C552
FEATURES
•
80C51 central processing unit
•
8k
×
8 ROM expandable externally to 64 kbytes
•
ROM code protection
•
An additional 16-bit timer/counter coupled to four capture registers
and three compare registers
DESCRIPTION
The 80C552/83C552 (hereafter generically referred to as 8XC552)
Single-Chip 8-Bit Microcontroller is manufactured in an advanced
CMOS process and is a derivative of the 80C51 microcontroller
family. The 8XC552 has the same instruction set as the 80C51.
Three versions of the derivative exist:
•
83C552—8 kbytes mask programmable ROM
•
•
•
•
•
•
•
•
•
•
•
Two standard 16-bit timer/counters
256
×
8 RAM, expandable externally to 64 kbytes
Capable of producing eight synchronized, timed outputs
A 10-bit ADC with eight multiplexed analog inputs
Two 8-bit resolution, pulse width modulation outputs
Five 8-bit I/O ports plus one 8-bit input port shared with analog
inputs
I
2
C-bus serial I/O port with byte oriented master and slave
functions
Full-duplex UART compatible with the standard 80C51
On-chip watchdog timer
Three speed ranges:
–
3.5 to 16 MHz
–
3.5 to 24 MHz (ROM, ROMless only)
Three operating ambient temperature ranges:
–
P83C552xBx: 0
°C
to +70
°C
–
P83C552xFx: –40
°C
to +85
°C
(XTAL frequency max. 24 MHz)
–
P83C552xHx: –40
°C
to +125
°C
(XTAL frequency max. 16 MHz)
•
•
80C552—ROMless version of the 83C552
87C552—8 kbytes EPROM (described in a separate chapter)
The 8XC552 contains a non-volatile 8k
×
8 read-only program
memory (83C552), a volatile 256
×
8 read/write data memory, five
8-bit I/O ports, one 8-bit input port, two 16-bit timer/event counters
(identical to the timers of the 80C51), an additional 16-bit timer
coupled to capture and compare latches, a 15-source,
two-priority-level, nested interrupt structure, an 8-input ADC, a dual
DAC pulse width modulated interface, two serial interfaces (UART
and I
2
C-bus), a “watchdog” timer and on-chip oscillator and timing
circuits. For systems that require extra capability, the 8XC552 can
be expanded using standard TTL compatible memories and logic.
In addition, the 8XC552 has two software selectable modes of
power reduction—idle mode and power-down mode. The idle mode
freezes the CPU while allowing the RAM, timers, serial ports, and
interrupt system to continue functioning. The power-down mode
saves the RAM contents but freezes the oscillator, causing all other
chip functions to be inoperative.
The device also functions as an arithmetic processor having
facilities for both binary and BCD arithmetic plus bit-handling
capabilities. The instruction set consists of over 100 instructions: 49
one-byte, 45 two-byte, and 17 three-byte. With a 16 MHz (24 MHz)
crystal, 58% of the instructions are executed in 0.75
µs
(0.5
µs)
and
40% in 1.5
µs
(1
µs).
Multiply and divide instructions require 3
µs
(2
µs).
LOGIC SYMBOL
V
SS
V
DD
XTAL1
XTAL2
EA
ALE
PSEN
AV
SS
AV
DD
AVref+
AVref–
STADC
PWM0
PWM1
PORT 0
LOW ORDER
ADDRESS AND
DATA BUS
ADC0-7
PORT 5
CT0I
CT1I
CT2I
CT3I
T2
RT2
SCL
SDA
PORT 2
PORT 1
HIGH ORDER
ADDRESS AND
DATA BUS
CMSR0-5
PORT 4
RxD/DATA
TxD/CLOCK
INT0
INT1
T0
T1
WR
RD
CMT0
CMT1
RST
EW
PORT 3
SU01691
2002 Sep 03
2
853-1467 28849
Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
80C552/83C552
PIN CONFIGURATIONS
Plastic Leaded Chip Carrier
P4.2/CMSR2
P4.1/CMSR1
P4.0/CMSR0
P5.0/ADC0
P5.4/ADC4
P5.5/ADC5
P5.6/ADC6
P5.1/ADC1
P5.2/ADC2
P5.3/ADC3
P5.7/ADC7
62
PWM1
PWM0
STADC
9
P4.3/CMSR3 10
P4.4/CMSR4
11
8
7
6
5
4
3
2
V
DD
EW
1
68
67
66
65
64
63
61
60 AV
SS
59 AV
REF+
58 AV
REF–
57 P0.0/AD0
56 P0.1/AD1
55 P0.2/AD2
54 P0.3/AD3
53 P0.4/AD4
P4.5/CMSR5 12
P4.6/CMT0 13
P4.7/CMT1 14
RST 15
P1.0/CT0I 16
P1.1/CT1I 17
P1.2/CT2I 18
P1.3/CT3I 19
P1.4/T2 20
P1.5/RT2 21
P1.6/SCL 22
P1.7/SDA 23
P3.0/RxD 24
P3.1/TxD 25
P3.2/INT0 26
27
P3.3/INT1
28
P3.4/T0
29
P3.5/T1
30
P3.6/WR
31
P3.7/RD
32
NC*
33
NC*
34
XTAL2
35
XTAL1
36
V
SS
37
V
SS
38
NC*
39
P2.0/A08
40
P2.1/A09
41
P2.2/A10
42
P2.3/A11
43
P2.4/A12
PLASTIC LEADED CHIP CARRIER
AV
DD
52 P0.5/AD5
51 P0.6/AD6
50 P0.7/AD7
49 EA
48
ALE
47 PSEN
46
P2.7/A15
45 P2.6/A14
44 P2.5/A13
SU00932
* Do not connect.
2002 Sep 03
3
Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
80C552/83C552
Plastic Quad Flat Pack
P4.0/SMSR0
P5.3/ADC3
P5.4/ADC4
P5.5/ADC5
66
P5.0/ADC0
P5.1/ADC1
P5.2/ADC2
P5.6/ADC6
65
64 P5.7/ADC7
63 AV
DD
62 NC*
61 AV
SS
60 AV
REF+
59 AV
REF–
58 P0.0/AD0
57 P0.1/AD1
56 P0.2/AD2
55 P0.3/AD3
54 P0.4/AD4
53 P0.5/AD5
PWM1
PWM0
STADC
NC*
NC*
80
P4.1/CMSR1
P4.2/CMSR2
NC*
P4.3/CMSR3
P4.4/CMSR4
P4.5/CMSR5
P4.6/CMT0
P4.7/CMT1
RST
1
2
3
4
5
6
7
8
9
79
78
77
76
75
74
73
72
V
DD
EW
IC
71
70
69
68
67
P1.0/CT0I 10
P1.1/CT1I
11
P1.2/CT2I 12
PLASTIC QUAD FLAT PACK
P1.3/CT3I
13
52
P0.6/AD6
P1.4/T2 14
P1.5/RT2 15
P1.6/SCL 16
P1.7/SDA 17
P3.0/RxD 18
P3.1/TxD 19
P3.2/INT0 20
NC* 21
NC* 22
P3.3/INT1 23
PP3.4/T0 24
25
P3.5/T1
26
P3.6/WR
27
P3.7/RD
28
NC*
29
NC*
30
NC*
31
XTAL2
32
XTAL1
33
IC
34
V
SS
35
V
SS
36
V
SS
37
NC*
38
P2.0/A08
39
P2.1/A09
40
P2.2/A10
51 P0.7/AD7
50
EA
49 ALE
48 PSEN
47 P2.7/A15
46 P2.6/A14
45 P2.5/A13
44 NC*
43 NC*
42 P2.4/A12
41 P2.3/A11
SU00931
* Do not connect.
IC = Internally connected (do not use).
2002 Sep 03
4
Philips Semiconductors
Product data
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
80C552/83C552
BLOCK DIAGRAM
T0
3
T1
3
INT0
3
INT1
3
V
DD
V
SS
PWM0 PWM1
AV
SS
AV
REF
ADC0-7 SDA
5
1
SCL
1
– +
AV
DD
STADC
XTAL1
XTAL2
EA
ALE
PSEN
3
3
RD
0
AD0-7
2
A8-15
PARALLEL I/O
PORTS AND
EXTERNAL BUS
SERIAL
UART
PORT
8-BIT
PORT
FOUR
16-BIT
CAPTURE
LATCHES
16
WR
T0, T1
TWO 16-BIT
TIMER/EVENT
COUNTERS
PROGRAM
MEMORY
8k x 8 ROM
DATA
MEMORY
256 x 8 RAM
DUAL
PWM
ADC
SERIAL
I
2
C PORT
CPU
80C51 CORE
EXCLUDING
ROM/RAM
8-BIT INTERNAL BUS
T2
16-BIT
TIMER/
EVENT
COUNTERS
16
T2
16-BIT
COMPARA-
TORS
wITH
REGISTERS
COMPARA-
TOR
OUTPUT
SELECTION
T3
WATCHDOG
TIMER
3
P0
P1
P2
P3
TxD
3
RxD
P5
P4
CT0I-CT3I
1
1
T2
RT2
1
4
CMSR0-CMSR5
CMT0, CMT1
RST
EW
0
1
2
ALTERNATE FUNCTION OF PORT 0
ALTERNATE FUNCTION OF PORT 1
ALTERNATE FUNCTION OF PORT 2
3
4
5
ALTERNATE FUNCTION OF PORT 3
ALTERNATE FUNCTION OF PORT 4
ALTERNATE FUNCTION OF PORT 5
SU01692
2002 Sep 03
5
DSP 与 ARM 处理器
