INTEGRATED CIRCUITS
80C851/83C851
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
Product specification
Supersedes data of 1992 Nov 25
IC20 Data Handbook
1998 Jul 03
Philips
Semiconductors
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
80C851/83C851
DESCRIPTION
The Philips 80C851/83C851 is a
high-performance microcontroller fabricated
with Philips high-density CMOS technology.
The 80C851/83C851 has the same
instruction set as the 80C51. The Philips
CMOS technology combines the high speed
and density characteristics of HMOS with the
low power attributes of CMOS. The Philips
epitaxial substrate minimizes latch-up
sensitivity.
The 80C851/83C851 contains a 4k
×
8 ROM
with mask-programmable ROM code
protection, a 128
×
8 RAM, 256
×
8
EEPROM, 32 I/O lines, two 16-bit
counter/timers, a seven-source, five vector,
two-priority level nested interrupt structure,
a serial I/O port for either multi-processor
communications, I/O expansion or full duplex
UART, and on-chip oscillator and clock
circuits.
In addition, the 80C851/83C851 has two
software selectable modes of power
reduction — idle mode and power-down
mode. The idle mode freezes the CPU while
allowing the RAM, timers, serial port, and
interrupt system to continue functioning. The
power-down mode saves the RAM and
EEPROM contents but freezes the oscillator,
causing all other chip functions to be
inoperative.
FEATURES
•
80C51 based architecture
–
4k
×
8 ROM
–
128
×
8 RAM
–
Two 16-bit counter/timers
–
Full duplex serial channel
–
Boolean processor
•
Non-volatile 256
×
8-bit EEPROM
(electrically erasable programmable read
only memory)
–
On-chip voltage multiplier for erase/write
–
10,000 erase/write cycles per byte
–
10 years non-volatile data retention
–
Infinite number of read cycles
–
User selectable security mode
–
Block erase capability
•
Mask-programmable ROM code protection
•
Memory addressing capability
–
64k ROM and 64k RAM
•
Power control modes:
–
Idle mode
–
Power-down mode
•
CMOS and TTL compatible
•
1.2 to 16MHz or 3.5 to 24MHz
•
Three package styles
•
Three temperature ranges
•
ROM code protection
ORDERING INFORMATION
PHILIPS
PART ORDER NUMBER
PART MARKING
ROMless
Version
P80C851 FBP
P80C851 IBP
P80C851 FBA
P80C851 IBA
P80C851 FBB
P80C851 IBB
P80C851 FFP
P80C851 FFA
P80C851 FFB
P80C851 FHP
P80C851 FHA
P80C851 FHB
ROM Version
P83C851 FBP
P83C851 IBP
P83C851 FBA
P83C851 IBA
P83C851 FBB
P83C851 IBB
P83C851 FFP
P83C851 FFA
P83C851 FFB
P83C851 FHP
P83C851 FHA
P83C851 FHB
S80C851-5N40
S80C851-5A44
S80C851-5B44
S80C851-6N40
S80C851-6A44
S80C851-6B44
S83C851-5N40
S83C851-5A44
S83C851-5B44
S83C851-6N40
S83C851-6A44
S83C851-6B44
S80C851-4B44
S83C851-4B44
S80C851-4A44
S83C851-4A44
NORTH AMERICA PHILIPS
PART ORDER NUMBER
ROMless
Version
S80C851-4N40
ROM Version
S83C851-4N40
TEMPERATURE RANGE
°
C
AND PACKAGE
0 to +70, Plastic Dual In-line Package
0 to +70, Plastic Dual In-line Package
0 to +70, Plastic Leaded Chip Carrier
0 to +70, Plastic Leaded Chip Carrier
0 to +70, Plastic Quad Flat Pack
0 to +70, Plastic Quad Flat Pack
–40 to +85, Plastic Dual In-line Package
–40 to +85, Plastic Leaded Chip Carrier
–40 to +85, Plastic Quad Flat Pack
–40 to +125, Plastic Dual In-line Package
–40 to +125, Plastic Leaded Chip Carrier
–40 to +125, Plastic Quad Flat Pack
FREQ.
(MHz)
1.2 to 16
3.5 to 24
1.2 to 16
3.5 to 24
1.2 to 16
3.5 to 24
1.2 to 16
1.2 to 16
1.2 to 16
1.2 to 16
1.2 to 16
1.2 to 16
DRAWING
NUMBER
SOT129-1
SOT129-1
SOT187-1
SOT187-1
SOT307-2
SOT307-2
SOT129-1
SOT187-1
SOT307-2
SOT129-1
SOT187-1
SOT307-2
1998 Jul 03
2
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
80C851/83C851
BLOCK DIAGRAM
FREQUENCY
REFERENCE
XTAL2
XTAL1
COUNTERS
T0
T1
OSCILLATOR
AND
TIMING
PROGRAM
MEMORY
(4K x 8 ROM)
DATA
MEMORY
(128 x 8 RAM)
TWO 16-BIT
TIMER/EVENT
COUNTERS
EEPROM
(256 x 8)
CPU
INTERNAL
INTERRUPTS
64K BYTE BUS
EXPANSION
CONTRTOL
PROGRAMMABLE I/O
PROG SERIAL PORT
FULL DUPLEX UART
SYNCHRONOUS SHIFT
INT0
INT1
CONTROL
PARALLEL PORTS,
ADDRESS/DATA BUS
AND I/O PINS
SERIAL IN
SERIAL OUT
EXTERNAL
INTERRUPTS
SHARED WITH
PORT 3
LOGIC SYMBOL
V
DD
XTAL1
PORT 0
ADDRESS AND
DATA BUS
V
SS
XTAL2
SECONDARY FUNCTIONS
RST
EA
PSEN
ALE
RxD
TxD
INT0
INT1
T0
T1
WR
RD
PORT 3
PORT 2
PORT 1
ADDRESS BUS
1998 Jul 03
3
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
80C851/83C851
PIN CONFIGURATIONS
PLASTIC LEADED CHIP
CARRIER PIN FUNCTIONS
6
1
40
PLASTIC QUAD FLAT PACK
PIN FUNCTIONS
44
34
P1.0 1
P1.1 2
P1.2 3
P1.3 4
P1.4 5
P1.5 6
P1.6 7
P1.7 8
RST 9
RxD/P3.0 10
TxD/P3.1 11
INT0/P3.2 12
INT1/P3.3 13
T0/P3.4 14
T1/P3.5 15
WR/P3.6 16
RD/P3.7 17
XTAL2 18
XTAL1 19
V
SS
20
DUAL
IN-LINE
PACKAGE
40 V
DD
39 P0.0/AD0
7
38 P0.1/AD1
37 P0.2/AD2
36 P0.3/AD3
35 P0.4/AD4
34 P0.5/AD5
33 P0.6/AD6
32 P0.7/AD7
31 EA
30 ALE
29 PSEN
28 P2.7/A15
27 P2.6/A14
26 P2.5/A13
25 P2.4/A12
24 P2.3/A11
23 P2.2/A10
22 P2.1/A9
21 P2.0/A8
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
39
PLASTIC
LEADED
CHIP
CARRIER
22
17
39
1
33
PLCC
PQFP
29
11
23
18
28
12
Function
NC*
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15
PSEN
ALE
NC*
EA
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
V
DD
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Function
P1.5
P1.6
P1.7
RST
P3.0/RxD
NC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7RD
XTAL2
XTAL1
V
SS
NC*
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
Pin
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
22
Function
P2.5/A13
P2.6/A14
P2.7/A15
PSEN
ALE
NC*
EA
P0.7/AD7
P0.6/AD6
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
P0.1/AD1
P0.0/AD0
V
DD
V
SS
P1.0
P1.1
P1.2
P1.3
P1.4
Function
NC*
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
P3.0/RxD
NC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
V
SS
Pin
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
6
1
40
7
* NO INTERNAL CONNECTION
* NO INTERNAL CONNECTION
17
29
18
28
44
34
1
PLASTIC
QUAD
FLAT
PACK
11
33
23
12
22
1998 Jul 03
4
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
80C851/83C851
PIN DESCRIPTION
PIN NO.
MNEMONIC
V
SS
V
DD
P0.0–0.7
DIP
20
40
39–32
LCC
22
44
43–36
QFP
16, 39
38
37–30
TYPE
I
I
I/O
Ground:
0V reference.
Power Supply:
This is the power supply voltage for normal, idle, and power-down
operation.
Port 0:
Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to
them float and can be used as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program and data memory.
In this application, it uses strong internal pull-ups when emitting 1s.
Port 1:
Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have
1s written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 1 pins that are externally pulled low will source current because of the
internal pull-ups. (See DC Electrical Characteristics: I
IL
).
Port 2:
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have
1s written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 2 pins that are externally being pulled low will source current because of the
internal pull-ups. (See DC Electrical Characteristics: I
IL
). Port 2 emits the high-order
address byte during fetches from external program memory and during accesses to
external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it
uses strong internal pull-ups when emitting 1s. During accesses to external data memory
that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function
register.
Port 3:
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have
1s written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 3 pins that are externally being pulled low will source current because of the
pull-ups. (See DC Electrical Characteristics: I
IL
). Port 3 also serves the special features
of the SC80C51 family, as listed below:
RxD (P3.0):
Serial input port
TxD (P3.1):
Serial output port
INT0 (P3.2):
External interrupt
INT1 (P3.3):
External interrupt
T0 (P3.4):
Timer 0 external input
T1 (P3.5):
Timer 1 external input
WR (P3.6):
External data memory write strobe
RD (P3.7):
External data memory read strobe
Reset:
A high on this pin for two machine cycles while the oscillator is running, resets the
device. An internal diffused resistor to V
SS
permits a power-on reset using only an
external capacitor to V
DD
.
Address Latch Enable:
Output pulse for latching the low byte of the address during an
access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6
the oscillator frequency, and can be used for external timing or clocking. Note that one
ALE pulse is skipped during each access to external data memory.
Program Store Enable:
The read strobe to external program memory. When the device
is executing code from the external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access to
external data memory. PSEN is not activated during fetches from internal program
memory.
External Access Enable:
If during a RESET, EA is held at TTL, level HIGH, the CPU
executes out of the internal program memory ROM provided the Program Counter is less
than 4096. If during a RESET, EA is held a TTL LOW level, the CPU executes out of
external program memory. EA is not allowed to float.
Crystal 1:
Input to the inverting oscillator amplifier and input to the internal clock
generator circuits.
Crystal 2:
Output from the inverting oscillator amplifier.
NAME AND FUNCTION
P1.0–P1.7
1–8
2–9
40–44,
1–3
I/O
P2.0–P2.7
21–28
24–31
18–25
I/O
P3.0–P3.7
10–17
11,
13–19
5,
7–13
I/O
10
11
12
13
14
15
16
17
RST
9
11
13
14
15
16
17
18
19
10
5
7
8
9
10
11
12
13
4
I
O
I
I
I
I
O
O
I
ALE
30
33
27
I/O
PSEN
29
32
26
O
EA
31
35
29
I
XTAL1
XTAL2
19
18
21
20
15
14
I
O
1998 Jul 03
5
