P89V660/662/664
8-bit 80C51 5 V low power 16 kB/32 kB/64 kB flash
microcontroller with 512 B/1 kB/2 kB RAM, dual I
2
C-bus, SPI
Rev. 3.1 — 17 October 2011
Product data sheet
1. General description
The P89V660/662/664 are 80C51 microcontrollers with 16 kB/32 kB/64 kB flash and
512 B/1 kB/2 kB of data RAM. These devices are designed to be drop-in and software
compatible replacements for the P89C660/662/664 devices. Both the In-System
Programming (ISP) and In-Application Programming (IAP) boot codes are upward
compatible.
Additional features of the P89V660/662/664 devices when compared to the
P89C660/662/664 devices are the inclusion of a secondary 100 kHz byte-wide I
2
C-bus
interface, an SPI interface, four addition I/O pins (Port 4), and the ability to erase code
memory in 128-byte pages.
The IAP capability combined with the 128-byte page size allows for efficient use of the
code memory for non-volatile data storage.
2. Features and benefits
2.1 Principal features
Dual 100 kHz byte-wide I
2
C-bus interfaces
128-byte page erase for efficient use of code memory as non-volatile data storage
0 MHz to 40 MHz operating frequency in 12x mode, 20 MHz in 6x mode
16 kB/32 kB/64 kB of on-chip flash user code memory with ISP and IAP
512 B/1 kB/2 kB RAM
SPI (Serial Peripheral Interface) and enhanced UART
PCA (Programmable Counter Array) with PWM and Capture/Compare functions
Three 16-bit timers/counters
Four 8-bit I/O ports, one 4-bit I/O port
WatchDog Timer (WDT)
2.2 Additional features
30 ms page erase, 150 ms block erase
Support for 6-clock (default) or 12-clock mode selection via ISP or parallel programmer
PLCC44 and TQFP44 packages
Ten interrupt sources with four priority levels
Second DPTR register
Low EMI mode (ALE inhibit)
Power-down mode with external interrupt wake-up
NXP Semiconductors
P89V660/662/664
80C51 with 512 B/1 kB/2 kB RAM, dual I
2
C-bus, SPI
Idle mode
2.3 Comparison to the P89C660/662/664 devices
SPI interface.
The P89V660/662/664 devices include an SPI interface that was not
present on the P89C660/662/664 devices.
Dual I2C-bus interfaces.
The P89V660/662/664 devices have two I
2
C-bus interfaces.
The P89C660/662/664 devices have one.
More I/O pins.
The P89V660/662/664 devices have an additional four-bit I/O port,
Port 4.
The
6x/12x mode
on theP89V660/662/664 devices is
programmable
and erasable
using ISP
and IAP as well as parallel programmer mode. The P89C660/662/664
devices could only be switched using parallel programmer mode.
Smaller block sizes.
The smallest block size on the P89C660/662/664 devices was
8 kB. The P89V660/662/664 devices have a page size of 128 B. These small pages
can be erased and reprogrammed using IAP function calls making use of the code
memory for non-volatile data storage practical. Each page erase is 30 ms or less. The
IAP and ISP code in P89V660/662/664 devices support these 128-byte page
operations. In addition, the IAP and ISP code uses multiple page erase operations to
emulate the erasing of the larger block sizes (8 kB and 16 kB to maintain firmware
compatibility).
Status bit versus Status byte.
The P89V660/662/664 devices used a Status byte to
control the automatic entry into ISP mode following a reset. On the P89V660/662/664
devices this has changed to a single Status bit. Since the ISP entry was based on the
zero/non-zero value of the Status byte this is an almost identical operation on the
P89V660/662/664 devices.
Faster block erase.
The erase time for the entire user code memory of the
P89V660/662/664 devices is 150 ms.
3. Ordering information
Table 1.
Ordering information
Package
Name
P89V662FA
P89V662FBC
P89V664FA
P89V664FBC
PLCC44
TQFP44
PLCC44
TQFP44
Description
plastic leaded chip carrier; 44 leads
plastic thin quad flat package; 44 leads; body
10
10
1.0 mm
plastic leaded chip carrier; 44 leads
plastic thin quad flat package; 44 leads; body
10
10
1.0 mm
Version
SOT187-2
SOT376-1
SOT187-2
SOT376-1
Type number
P89V660_662_664
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3.1 — 17 October 2011
2 of 90
NXP Semiconductors
P89V660/662/664
80C51 with 512 B/1 kB/2 kB RAM, dual I
2
C-bus, SPI
3.1 Ordering options
Table 2.
Ordering options
Flash memory
32 kB
32 kB
64 kB
64 kB
Temperature range
40 C
to +85
C
Frequency
0 MHz to 40 MHz
Type number
P89V662FA
P89V662FBC
P89V664FA
P89V664FBC
4. Block diagram
P89V660/662/664
HIGH PERFORMANCE 80C51 CPU
16 kB/32 kB/64 kB
CODE FLASH
0.5 kB/1 kB/ 2 kB
DATA RAM
UART
internal
bus
SPI
TXD
RXD
SPICLK
MOSI
MISO
SS
T0
T1
T2
T2EX
P4[7:0]
PORT 4
TIMER 0
TIMER 1
P3[7:0]
PORT 3
TIMER 2
P2[7:0]
PORT 2
PCA
PROGRAMMABLE
COUNTER ARRAY
CEX[4:0]
P1[7:0]
PORT 1
WATCHDOG TIMER
P0[7:0]
XTAL1
PORT 0
PRIMARY I
2
C-BUS
SCL
SDA
SCL_1
SDA_1
CRYSTAL
OR
RESONATOR
OSCILLATOR
XTAL2
SECONDARY I
2
C-BUS
002aab908
Fig 1. Block diagram
P89V660_662_664
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3.1 — 17 October 2011
3 of 90
NXP Semiconductors
P89V660/662/664
80C51 with 512 B/1 kB/2 kB RAM, dual I
2
C-bus, SPI
5. Pinning information
5.1 Pinning
P1[4]/CEX1
P1[3]/CEX0
P4[2]/MOSI
P1[1]/T2EX
43 P0[0]/AD0
42 P0[1]/AD1
41 P0[2]/AD2
40 P0[3]/AD3
39 P0[4]/AD4
38 P0[5]/AD5
37 P0[6]/AD6
36 P0[7]/AD7
35 EA
34 P4[1]/SDA_1/MISO
33 ALE/PROG
32 PSEN
31 P2[7]/A15
30 P2[6]/A14
29 P2[5]/A13
P3[6]/WR 18
P3[7]/RD 19
XTAL2 20
XTAL1 21
V
SS
22
P4[0]/SCL_1/SPICLK 23
P2[0]/A8 24
P2[1]/A9 25
P2[2]/A10 26
P2[3]/A11 27
P2[4]/A12 28
002aab909
P1[2]/ECI
P1[0]/T2
2
P1[5]/CEX2
P1[6]/SCL
P1[7]/SDA
7
8
9
RST 10
P3[0]/RXD 11
P4[3]/SS 12
P3[1]/TXD 13
P3[2]/INT0 14
P3[3]/INT1 15
P3[4]/T0/CEX3 16
P3[5]/T1/CEX4 17
P89V660/662/664
Fig 2. PLCC44 pin configuration
P89V660_662_664
All information provided in this document is subject to legal disclaimers.
44 V
DD
6
5
4
3
1
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3.1 — 17 October 2011
4 of 90
NXP Semiconductors
P89V660/662/664
80C51 with 512 B/1 kB/2 kB RAM, dual I
2
C-bus, SPI
44 P1[4]/CEX1
43 P1[3]/CEX0
39 P4[2]/MOSI
41 P1[1]/T2EX
37 P0[0]/AD0
36 P0[1]/AD1
35 P0[2]/AD2
P1[5]/CEX2
P1[6]/SCL
P1[7]/SDA
RST
P3[0]/RXD
P4[3]/SS
P3[1]/TXD
P3[2]/INT0
P3[3]/INT1
1
2
3
4
5
6
7
8
9
34 P0[3]/AD3
33 P0[4]/AD4
32 P0[5]/AD5
31 P0[6]/AD6
30 P0[7]/AD7
29 EA
28 P4[1]/SDA_1/MISO
27 ALE/PROG
26 PSEN
25 P2[7]/A15
24 P2[6]/A14
23 P2[5]/A13
P2[4]/A12 22
002aab910
42 P1[2]/ECI
40 P1[0]/T2
V
SS
16
P89V660/662/664
P3[4]/T0/CEX3 10
P3[5]/T1/CEX4 11
P3[6]/WR 12
P3[7]/RD 13
XTAL2 14
XTAL1 15
P4[0]/SCL_1/SPICLK 17
P2[0]/A8 18
P2[1]/A9 19
P2[2]/A10 20
P2[3]/A11 21
Fig 3. TQFP44 pin configuration
P89V660_662_664
All information provided in this document is subject to legal disclaimers.
38 V
DD
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3.1 — 17 October 2011
5 of 90
