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APEX Signal, A Division of NAI, Inc.

PC-77DS1

EIGHT

(1.2 VA)

DIGITAL

SYNCHRO/RESOLVER CONVERTERS

4 TWO-SPEED or 8 SINGLE-SPEED or COMBINATION (PROGRAMMABLE)

16 BIT RESOLUTION; To .0083° ACCURACY;

ON-BOARD PROGRAMMABLE REFERENCE SUPPLY

SELF TEST

and

Programmable Rotation

FEATURES:

•

16-bit resolution

30 arc-seconds accuracy

360 Hz to 10 kHz operation

1.2 VA drive capability

2,4,6 or 8-channel versions available

Programmable 2-speed ratios (2 to 255) and angle rotation

Continuous background BIT testing with Reference and Signal loss detection

Power-On Self-Test (POST)

Outputs can be turned ON/OFF

Either internal or external

±12

VDC supply

Optional on-board programmable reference supply

Watchdog timer and soft reset

Transformer isolated

No adjustments or trimming required

Part Number, S/N, Date Code and Revision in permanent memory

DESCRIPTION:

This high density intelligent DSP-based card incorporates up to eight separate transformer isolated Digital-to-

Synchro/Resolver converters with 1.2 VA drive, extensive diagnostics, signal & reference loss detection and optional 5

VA reference supply. Either one common or eight separate reference inputs can be specified. Each output can be

turned ON or OFF via the bus. Two-speed configuration and constant rotation that includes a start and a stop angle

can be programmed. Transformer isolation enables user to ground one of the outputs without affecting performance.

The optional on−board reference supply is field programmable for both voltage and frequency. A watchdog timer is

provided to monitor the processor. This model will drive passive loads such as CT's etc. Part Number, S/N, Date

Code, and Revision are located in permanent memory. The

±12VDC

is normally derived from the backplane, but

jumpers are supplied to permit the card to be powered from external supplies.

Major diagnostics are incorporated to offer substantial improvements to system reliability because the user is alerted

(within 5 seconds) to channel malfunctions. This approach reduces bus traffic because the Status Registers do not

require constant polling. See Programming Instructions for further details.

The D2 Test initiates automatic background BIT Testing that compares the output of each channel against the

commanded input to a test accuracy of 0.05° and monitors each Output and Reference. Results are available in

Status registers. The testing is totally transparent to the user, requires no external programming, has no effect on the

standard operation of this card and can be enabled or disabled via the bus.

The D3 Test starts a BIT Test that generates and tests 72 different angles, to a testing accuracy of 0.05°. Results can

be read from Status Registers. External reference is required and testing requires no external programming, and can

be Initiated or terminated via the bus. CAUTION: Outputs must be ON and are therefore active during this test.

Check connected loads for possible interaction.

Power-On Self-Test (POST), if enabled, initiates the D3 Test upon turn-on and is enabled/disabled via the bus.

Apex Signal,

A Division of NAI, Inc.

170 Wilbur Place, Bohemia, NY, 11716,USA

631.567.1100/631.567.1823(fax)

www.naii.com

/ e-mail:sales@naii.com

3-20-01

Code:OVGU1

S 77 DS1 A001 REV A 1.2

Page 1 of 8

SPECIFICATIONS

(applies to each Channel)

Resolution:

Accuracy:

Output format:

Output voltage:

Output load:

Regulation:

Ratio:

Rotation:

16 bits (.0055°)

30 arc-seconds (.008°) at 0.3 VA

±1 arc-minute (.017°) at 1.2 VA. No load to full load

See part number, transformer isolated

See code table and part number.

1.2 VA max./channel. Short circuit protected (5000

Ω

reactive at 90 V

L-L

Synchro,

Ω

reactive at 11.8 V

L-L

Synchro, 110

Ω

reactive at 11.8 V

L-L

Resolver)

5% maximum, no load to Full load

Set any ratio between 2 and 255

Continuous rotation or programmable Start and Stop angles. 0 to

±13.6

RPS with a

resolution of 0.15°/sec. Step size is 16 bits (0.0055)° up to 1.5 RPS, then linearly increases

to 12 bits (0.088°) at 13.6 RPS.

(See code table and part number) Transformer isolated. 1 ma max./channel

360 Hz to 10 kHz (see code table and part number)

5° max. between output and reference.

Less than 100 microseconds

+ 5 VDC at 0.4 A

±12 VDC at 1.6 A average, 4 A peak (for 8 channels). Power supplies must be able to

supply peak power without current limiting.

0°C to +70°C. Storage temperature: -55°C to +85°C.

4.5 x13.5 x 0.74 (11.43 x 34.29 x 1.88 cm)

12 oz. (.605 kg)

Optional (see part number).

2.0 to 28 Vrms programmable (Resolution 0.1Vrms) or 115 Vrms fixed. Accuracy

±2%,

360 Hz to 10 kHz

±1%

with 1 Hz resolution.

10% maximum, no load to full load.

5 VA max. at 40° min. inductive (see part number).

Reference input voltage:

Reference frequency:

Phase shift:

Settling time:

Power:

Temperature, operating:

Size:

Weight:

REFERENCE:

Voltage:

Frequency:

Regulation:

Output power:

PROGRAMMING:

I/O CONFIGURATION:

This card requires 32 consecutive addresses in the I/O address space on a 32-byte boundary. The base address is

switch settable in the 000-3E0 hex (0 to 992) address range.

ADDRESS= BASE + OFFSET

BASE

OFFSET A4 A3 A2 A1 A0

Decimal equiv.

SW1∗

SW2∗

128

SW3∗

256

SW4∗

512

SW5∗

∗

“1” = Off “0” = On

NOTE: Base addresses to avoid:

378-37F Parallel Printer Port 3B0-3BF Monochrome Display

3F8-3FF Asynch Comm I/O 3F0-3F7 Floppy Disk

Page 1 (1E = 0)

Ch.1

Ch.2

Ch.3

Ch.4

write

Ch.5

Ch.6

Ch.7

Ch.8

write

Freq. Lo

Freq. Hi

Eo Lo

Eo Hi

Status, Reference

Status, Signal

Status, Test

Test (D2) verification

write/read

read

write/read

Active channels

Save Lo

Save Hi

Page register = 0

write/read

write

Apex Signal,

A Division of NAI, Inc.

170 Wilbur Place, Bohemia, NY, 11716,USA

631.567.1100/631.567.1823(fax)

www.naii.com

/ e-mail:sales@naii.com

3-20-01

Code:OVGU1

S 7 7DS1 A001 REV A 1.2

Page 2 of 8

Page 2 (1E = 1)

Part # Lo

Part # Hi

Serial # Lo

Serial # Hi

Date code Lo

Date code Hi

Rev level Lo

read

Rev level Hi

Wrap-around Ch. 1 Lo

Wrap-around Ch. 1 Hi

Wrap-around Ch. 2 Lo

Wrap-around Ch. 2 Hi

Wrap-around Ch. 3 Lo

Wrap-around Ch. 3 Hi

read

Wrap-around Ch. 4 Lo read

Wrap-around Ch. 4 Hi read

Wrap-around Ch. 5 Lo read

Wrap-around Ch. 5 Hi read

Wrap-around Ch. 6 Lo read

Wrap-around Ch. 6 Hi read

Wrap-around Ch. 7 Lo read

1A/1B

1C/1D

Wrap-around Ch. 7 Hi

read

Wrap-around Ch. 8 Lo

read

Wrap-around Ch. 8 Hi

read

Power-on (POST)

read/write

Watchdog timer

read/write

Soft reset

write

Page register = 1

write

0F Stop angle Ch.8 Hi read/write

read

16 Rotation Complete

write/read

18 Rotation, Mode

1A Test Enable

write/read

1E Page register = 2

write

Page 3 (1E = 2)

Stop angle Ch.1 Lo

Stop angle Ch.1 Hi

Stop angle Ch.2 Lo

Stop angle Ch.2 Hi

Stop angle Ch.3 Lo

read/write

Stop angle Ch.3 Hi

Stop angle Ch.4 Lo

Stop angle Ch.4 Hi

Stop angle Ch.5 Lo

Stop angle Ch.5 Hi

read/write 0A

read/write 0B

read/write 0C

read/write 0D

read/write 0E

Stop angle Ch.6 Lo

Stop angle Ch.6 Hi

Stop angle Ch.7 Lo

Stop angle Ch.7 Hi

Stop angle Ch.8 Lo

read/write

Page 4 (1E = 3)

Rotate rate Ch.1 Lo read/write

Rotate rate Ch.1 Hi read/write

Rotate rate Ch.2 Lo read/write

Rotate rate Ch.2 Hi read/write

Rotate rate Ch.3 Lo read/write

Rotate rate Ch.3 Hi read/write

Rotate rate Ch.4 Lo read/write

Rotate rate Ch.4 Hi read/write

Rotate rate Ch.5 Lo read/write

Rotate rate Ch.5 Hi read/write

Rotate rate Ch.6 Lo read/write

Rotate rate Ch.6 Hi read/write

Rotate rate Ch.7 Lo read/write

Rotate rate Ch.7 Hi read/write

Rotate rate Ch.8 Lo read/write

Rotate rate Ch.8 Hi read/write

180

.703

Ch.8

.352

Ch.7

.176

Ch.6

Ratio, Ch.1/2 Lo read/write

Ratio, Ch.1/2 Hi read/write

Ratio, Ch.3/4 Lo read/write

Ratio, Ch.3/4 Hi read/write

Ratio, Ch.5/6 Lo read/write

Ratio, Ch.5/6 Hi read/write

Ratio, Ch.7/8 Lo read/write

Ratio, Ch.7/8 Hi read/write

2.813

.011

Ch.2

1.406

.0055

Ch.1

18 Outputs ON/OFF

1A Rotation, Initiate

1C Rotation, Stop

1E Page register = 3

read/write

write

Data Hi

Data Lo

Outputs, ON/OFF

Test Enable

Rotation, Mode

Rotation, INITIATE

Rotation, Stop

Rotation, completed

Active channels

Status, Reference

Status, Signal

Status, Test

22.5 11.25 5.625

.088 .044 .022

Ch.5 Ch.4 Ch.3

Power-On

System Reset

, all parameters are restored to last saved setup and if POST is enabled, a D3

test is initiated.

Enter Active Channels:

Set the bit, corresponding to each channel to be monitored during BIT testing, in the

Active Channel register at Page 1, 1Ah. “1”=active; “0”=not used. Omitting this step will produce false alarms

because unused channels will set faults.

Save Setup:

The current setup can be saved by writing 5555h to the Save Register at Page 1, 1C/1Dh. This

location will automatically clear to 0000h when the save is completed (within 5 seconds). When save is elected, all

parameters are saved, however, any parameter can be changed at will. Saving is optional. If not saved, reenter

parameters at each power up.

To restore factory shipped parameters, write AAAAh to the Save Register at Page 1, 1C/1Dh followed by system

reset. Note: After a SAVE or RESTORE, Poll Page 1, 1C/1Dh and do not perform any other operation until word is at

"0".

Read and Write Angle:

For single-speed applications (Ratio=1), in 16-bit mode, write 16-bit binary data (or 16-

bit 2’s compliment data) to address Page 1, 00h for Ch.1; to 02h for Ch.2 etc. In 8-bit mode, write to offset 00h/01h

to 0Eh/0Fh. The Write Registers are double buffered to prevent data ambiguity during 8-bit data transfer. Load data

into Hi byte register first, followed by the Lo byte. When reading the wrap around test angles, read the Hi byte first.

Apex Signal,

A Division of NAI, Inc.

170 Wilbur Place, Bohemia, NY, 11716,USA

631.567.1100/631.567.1823(fax)

www.naii.com

/ e-mail:sales@naii.com

3-20-01

Code:OVGU1

S 7 7DS1 A001 REV A 1.2

Page 3 of 8

Hi byte read holds Lo byte until read (ex. 330°=1110101010101011). For two-speed applications, write only to first

channel of channel pair (Coarse speed), and card will set angle of second channel (fine speed), to the Coarse angle

multiplied by the ratio. Note: writing to an input angle register will stop any rotation initiated on that channel.

Ratio:

Enter the desired ratio, as a binary number, in the Ratio Register corresponding to the pair of channels to be used as a

two-speed channel. Example: Single speed = 1; 36:1 = 100100.

ON/OFF:

Set the bit corresponding to each channel to be turned on, to “1” in Outputs On/Off Register at page 4,

18h. To turn OFF a channel, set corresponding bit to “0”. Default is OFF.

Read Wrap-Around Angles:

Read at addresses Page 2, 08h to 17h. AVAILABLE AT ALL TIMES.

Rotation Rate:

Write to the corresponding Rotation Rate register a 2’s compliment number representing the

desired rotation rate, LSB = 0.15°/sec. Ex: 12 RPS =. (12 x 360°/0.15° = 28800 = 7080h), -12 RPS = ( -12 x

360°/0.15° = -28800 = 8F80h). Step size is 16 bits (0.0055°) for up to 1.5 RPS, then linearly increases to 12 bits

(0.088°) at 13.6 RPS.

Rotation Mode, Continuous or Start/Stop:

For continuous rotation, set the corresponding channel bits to "1"

in the register at page 3, 18h. For rotation to cease at a designated stop angle, set the bit to "0".

Stop Angles:

Write 16-bit binary data to appropriate address at page 3, 00h to 0Fh. After a channel reaches the

stop angle, it will stop rotating and remain at that angle until a new input angle is set. If rotation is initiated again, the

angle will start rotating from the present angle.

Initiate Rotation:

First set the Rotation Rate Registers and Rotation Mode Register, for each channel that is to

rotate. Then, to start rotation for those channels, set the corresponding channel bit to a “1” in the Rotation Initiate

Stop Rotation:

Set the corresponding bit, for each channel to be stopped, to a “1” in the Rotation Stop Register at

page 4, 1Ch. Channel will remain at the stopped angle until new input angles are set, or rotation is again initiated.

Rotation Completed:

Read the Rotation Completed Register at page 3, 16h. Each bit corresponds to a given

channel. A "1" = rotation completed, "0"=rotation in process.

Power-On Self-Test (POST)

will initiate the D3 test on Power-On, if POST is enabled and saved. Enable by

writing "1" or Disable by writing "0" to POST register at page 2, 18h and then save setup.

D2 Test Enable:

Writing “1” to D2 of Test Enable Register at page 3, 1Ah initiates automatic background BIT

testing that checks the output accuracy of each channel, by comparing the measured output angle, before the output

transformer, to the commanded angle, and monitors each Reference and Signal. The status bits will be set to

indicate an accuracy problem or Signal/Reference loss and the results can be read from Status Registers within 2

seconds. A “0” deactivates this test. The testing is totally transparent to the user, requires no external programming,

has no effect on the standard operation of this card and can be enabled or disabled via the bus. Outputs must be ON

for test to function. Card will write 55h

(every 2 seconds)

to D2 Test Verify Register at page 1, 18h when D2 is

enabled. User can periodically clear to 0000h and then read page 1, 18h again, after 2 seconds, to verify that BIT

Testing is activated. This test continuously sequences between the eight channels on the card with each output

being measured for approx. 180 mSec. If the measured angle has an error greater the 0.05º, a flag will be set in the

appropriate register. If the input angle is stepped more then 0.05º during a test cycle, the test cycle will not generally

indicate an error.

D3 Test Enable:

Writing “1” to D3 of Test Enable Register at page 3, 1Ah initiates a BIT Test that generates and

tests 72 different angles to a test accuracy of 0.05°. External reference is required and outputs must be ON. The

Status bits will be set to indicate an accuracy problem or Signal or Reference loss. Results are available in Status

Registers. Test cycle takes about 30 seconds and D3 changes from “1” to “0” when test is complete. The testing

requires no external programming, and can be initiated or terminated via the bus. CAUTION: Outputs must be ON

during this test and are therefore active. Check connected loads for possible interaction.

Apex Signal,

A Division of NAI, Inc.

170 Wilbur Place, Bohemia, NY, 11716,USA

631.567.1100/631.567.1823(fax)

www.naii.com

/ e-mail:sales@naii.com

3-20-01

Code:OVGU1

S 7 7DS1 A001 REV A 1.2

Page 4 of 8

Status, Test:

Check the corresponding bit of the Test Status Register at page 1, 16h, for status of BIT Testing for

each active channel. A ”1” means Accuracy OK; “0” failed (test cycle takes 2 seconds for accuracy error).

Status, Ref:

Check the corresponding bit of the Ref Status Register at page 1, 14h, for status of the reference input

for each active channel. A ”1” =Ref. ON, “0” = Ref. Loss (Reference loss is detected after 2 seconds).

Status, Sig:

Check the corresponding bit of the Sig Status Register at page 1, 15h, for status of the input signals for

each active channel. A "1" = Signal ON, “0” = Signal loss (Signal loss is detected after 2 seconds).

Soft Reset

(Level sensitive): Writing “1” to page 2, 1Ch/1Dh initiates and holds software reset state. Then, writing “0” initiates

reboot (takes 400 ms). This function is equivalent to a power-on self-test.

Watchdog Timer:

This feature monitors the watchdog timer register at page 2, 1A/1Bh. When it detects that a

code has been received, that code will be inverted within 100 µSec. The inverted code stays in the register until

replaced by a new code. User, after 100 µSec. should look for the inverted code to confirm that the processor is

operating.

Optional Reference Supply:

For frequency, write a 16-bit word (Ex: 400 Hz = 1 1001 0000) to address page 1,

10/11h. For voltage, write an 16-bit word (Ex: 26.1 Vrms =1 0000 0101) with Lsb=0.1 Vrms, to address page 1,

12/13h. It is recommended that user program the required frequency before setting the output voltage.

Serial Number:

At page 2, 02/03h, is read as a 16-bit binary word.

Date Code:

Read as a decimal number at

page 2, 04/05h.

The four digits represent YYWW (Year,Year,Week.Week

Rev:

At page 1, 06/07h.

Example

15 14 13 12 11 10

DSP Rev 1.1

FPGA Rev 3

PC Rev

Front panel Connectors:

DC37P, Mate: DC37S

This connector is used when six (6) or fewer channels are specified

Ch. 1

RHi

RLo

Ch. 2

∗RHi

∗RLo

Ch. 3 Pin Ch. 4

10 S1

28 S2

9 S3

27 S4

∗RHi

∗RLo

Ch. 5

∗RHi

∗RLo

Ch. 6 Pin

1 Chassis

∗RHi

∗RLo

DD-50P, Mate: DD-50S

This connector is used when seven (7) or eight (8) channels are specified

Ch. 1

RHi

RLo

Ch. 2

∗RHi

∗RLo

Ch. 3 Pin Ch. 4

26 S1

42 S2

25 S3

41 S4

∗RHi

∗RLo

Ch. 5

∗RHi

∗RLo

Ch. 6 Pin Ch. 7 Pin Ch. 8

2 S1

8 S1

3 S2

9 S2

4 S3

10 S3

5 S4

11 S4

∗RHi

∗RLo

14 RefHi

1 RefLo

S4 pins used only with Resolvers.

Do not connect to any undesignated pins.

*These inputs are supplied as individual reference inputs ONLY when specified in the part number.

The Standard output connector for a 2, 4, or 6 channel card, is the 37 pin (DC-37P) connector, however the 50 pin

(DD-50P) connector can be ordered as an option, allowing separate pins for the output of the on board reference.

Apex Signal,

A Division of NAI, Inc.

170 Wilbur Place, Bohemia, NY, 11716,USA

631.567.1100/631.567.1823(fax)

www.naii.com

/ e-mail:sales@naii.com

3-20-01

Code:OVGU1

S 7 7DS1 A001 REV A 1.2

Page 5 of 8