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PC87413, PC87414, PC87416, PC87417 LPC ServerI/O for Servers and Workstations

July 2003

Revision 1.2

PC87413, PC87414, PC87416, PC87417

LPC ServerI/O for Servers and Workstations

General Description

The National Semiconductor

PC8741x family of LPC Serv-

erI/O devices (“PC8741x”) comprises highly integrated Ad-

vanced I/O products. The PC8741x is targeted for a wide

range of servers and workstations that use the Low Pin Count

(LPC) bus for the host interface and the serial ACCESS.bus

or SMBus

for the embedded controller interface.

The PC8741x features an X-Bus extension for read and write

operations over the X-Bus for both LPC and ACCESS.bus

cycles. Boot Flash and I/O devices can be accessed over this

X-Bus.

Embedded controllers can access the PC8741x and its X-Bus

via the ACCESS.bus or SMBus serial interface when V

exists, regardless of the LPC bus state. Some of the

PC8741x logical devices can be disabled, or their pins can be

floated, under control of the V

-powered serial bus.

The PC8741x provides a V

-powered high-frequency clock

for on-chip peripherals and for other V

-powered platform

components.

The PC8741x’s extended wake-up support complements the

chipset’s ACPI controller and the platform embedded control-

lers. The PC8741x can monitor the Power and Sleep buttons

and control the power supply of simple platforms that lack an

embedded controller. The System Wake-Up Control (SWC)

module is powered by V

and V

BAT

power supplies. It sup-

ports flexible wake-up and power-off request mechanisms in

any sleep state. It features Main and Standby power-on

elapsed-time counters.

The PC8741x also incorporates a Floppy Disk Controller

(FDC), two serial ports (UARTs), a Keyboard and Mouse

Controller (KBC), a Real-Time Clock (RTC), a fully compliant

IEEE 1284 Parallel Port, General-Purpose Input/Output

(GPIO) for a total of 51 ports and an Interrupt Serializer for

Parallel IRQs.

Outstanding Features

LPC Interface, based on Intel’s

LPC Interface Speciﬁ-

cation, Revision 1.0, September 29th, 1997

-powered access to modules through ACCESS.bus

or SMBus (PC87413

and PC87417)

X-Bus Extension for memory and I/O (PC87416

and

PC87417)

PC01 Revision 0.5 and ACPI Revision 1.0b compliant

ServerI/O modules: Parallel Port, FDC, two Serial Ports

(UARTs) and a Keyboard and Mouse Controller (KBC)

Y2K-compliant RTC with 242 bytes of RAM

51 GPIO ports with a variety of wake-up events

Extremely low current consumption in Battery Backup mode

128-pin PQFP package

Block Diagram

PC87417

(See page 5 for other PC8741x diagrams.)

Serial

Interface Interface

ServerI/O

Clock

Serial

Port 1

Serial

Port 2

Parallel Port

Interface

IEEE 1284

Parallel Port

Floppy Drive

Interface

Floppy Disk

Controller

LPC Serial

Keyboard Mouse

Interface Interface Interface IRQ

Keyboard &

Mouse Controller

LPC Bus

Interface

Device

Configuration

BAT

System

Wake-Up Control

Power

Timers

RTC

Internal Clocks

Clock

Generator

GPIO

Ports

X-Bus

Extension

ACCESS.bus

Interface

Wake-Up Power SCI &

Events Control SMI

Low-F High-F

32.768 KHz Clock Clock

X-Bus XIRQ

I/O

Interface

Ports

Clock Serial

Data

National Semiconductor and TRI-STATE are registered trademarks of National Semiconductor Corporation. All other

brand or product names are trademarks or registered trademarks of their respective holders.

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PC8741x

Features

Bus Interfaces

LPC Bus Interface

—

Based on Intel’s

LPC Interface Speciﬁcation Revi-

sion 1.0, September 29, 1997

—

Synchronous cycles using up to 33 MHz bus clock

—

8-bit I/O and Memory read and write cycles

—

Up to four 8-bit DMA channels

—

Serial IRQ

—

Supports bootable memory

—

Reset input

—

CLKRUN support

—

FWH Transaction support

ACCESS.bus (ACB) Interface (PC87413

and PC87417)

—

Enables a system controller to access the internal

functions and the X-Bus extension

—

Supports slave operation compatible with:

❏

Intel SMBus

❏

Conﬁguration Control (via LPC bus)

—

Compliant with

PC01 Speciﬁcation Revision 0.5,

November 2, 1999

—

Plug and Play (PnP) Conﬁguration register structure

—

Base Address strap to setup the address of the

Index-Data register pair

—

Flexible resource allocation for all logical devices:

❏

Relocatable base address

❏

15 IRQ routing options to serial IRQ

Up to four optional 8-bit DMA channels

—

ACCESS.bus control over pin multiplexing, module

disable and output TRI-STATE for all Legacy mod-

ules (PC87413

and PC87417)

Legacy Modules

ACCESS.bus

Serial Ports 1 and 2

—

Software compatible with the 16550A and the 16450

—

Supports shadow register for write-only bit monitoring

—

UART data rates up to 1.5 Mbaud

IEEE 1284-compliant Parallel Port

—

ECP, with Level 2 (14 mA sink and source output

buffers)

—

Software or hardware control

—

Enhanced Parallel Port (EPP) compatible with EPP

1.7 and EPP 1.9

—

Supports EPP as mode 4 of the Extended Control

—

Selection of internal pull-up or pull-down resistor for

Paper End (PE) pin

—

Supports a demand DMA mode mechanism and a

DMA fairness mechanism for improved bus utilization

—

Protection circuit that prevents damage to the

parallel port when a printer connected to it powers

up or is operated at high voltages, even if the device

is in power-down state

—

Optional outputs TRI-STATE by external pin

Floppy Disk Controller (FDC)

—

Programmable write protect

—

Supports FM and MFM modes

—

Supports Enhanced mode command for three-mode

Floppy Disk Drive (FDD)

—

Perpendicular recording drive support for 2.88 MB

—

Burst and Non-Burst modes

—

Full support for IBM Tape Drive Register (TDR) im-

plementation of AT and PS/2 drive types

—

16-byte FIFO

—

Error-free handling of data overrun and underrun

conditions during DMA transactions (i.e., does not

lose data or status bytes and is free of the NEC765A

bug)

—

Software compatible with the PC8477, which

contains a superset of the FDC functions in the

µDP8473,

NEC

µPD765A/B

and N82077

—

High-performance digital separator

—

Supports standard 5.25" and 3.5" FDDs

—

Supports up to four FDDs

—

Proprietary commands for read/write byte from/to:

❏

Internal register

❏

X-Bus I/O device

X-Bus memory device

—

Slave address:

❏

Two values selected by strap

❏

Programmable through the LPC bus

BAT

backed-up

—

Concurrent access with the LPC bus

—

powered

—

Optional internal pull-up on the ACBDAT and

ACBCLK pins

X-Bus Extension (PC87416

and PC87417)

—

Supports I/O and Memory read/write operations

—

8-bit data bus, 28-bit address

—

Multiplexed address-data lines:

❏

Four direct address lines

❏

Partial non-multiplexed option

—

Boot conﬁguration selected by straps

—

Four chip-select outputs, each supporting multiple

zones:

❏

Up to 32 MByte BIOS memory zones

❏

Up to 32 MByte user-deﬁned memory zones

Four user-deﬁned I/O zones

Test port and other I/O ports

Optional indirect addressing of memory

XRD-XEN or XWR-XR/W mode support

Supports both slow and fast devices

Accessible from both LPC and ACB buses

Programmable protection control over access from

the LPC bus

—

powered

—

External Interrupt support via XIRQ pin

—

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Revision1.2

PC8741x

Features

(Continued)

—

Supports fast tape drives (2 Mbps) and standard

tape drives (1 Mbps, 500 Kbps and 250 Kbps)

Power Management

Supports

ACPI Specification Revision 1.0b, Feb. 2, 1999

System Wake-Up Control (SWC)

—

Wake-up request on detection of:

❏

Preprogrammed Keyboard or Mouse sequence

❏

Keyboard and Mouse Controller (KBC)

—

8-bit microcontroller, software compatible with

8042AH and PC87911

—

Standard interface (60h, 64h, IRQ1 and IRQ12)

—

Supports two external swapable PS/2 interfaces for

keyboard and mouse

—

Five programmable, dedicated, open-drain I/O lines

(Fast GA20/P21, KBRST/P20, P12, P16, P17)

External modem ring from RI1 or RI2 on serial

ports

Predetermined RTC date and time alarm

General-Purpose Input Events from up to 16

GPIO pins

IRQs of internal logical devices

❏

General-Purpose Modules

❏

General-Purpose I/O (GPIO) Ports

—

51 GPIO Ports:

❏

Individually assigned to either LPC or ACB con-

trol (PC87413

and PC87417)

❏

46 individually conﬁgured as input or output

Five output-only

—

Programmable features for each output pin:

❏

Drive type (open-drain, push-pull or TRI-STATE)

❏

TRI-STATE on V

-fall detection for pins driving

-supplied devices

—

Optional routing of power-up request to SERIRQ,

SIOSMI, SIOSCI, PWBTOUT and ONCTL

—

Routing control per input/output event combination

—

Outputs enable/disable per event and system state

combination (ACPI Sx states)

—

Implements bank “b” of the ACPI registers

—

Suspend modes via software emulation (control)

—

Battery-backed event-logic conﬁguration

—

Power button support, featuring:

❏

On/Off control

❏

—

Programmable option for internal pull-up resistor on

each input pin

—

Lock option for the conﬁguration and data of each

output pin

—

16 GPIO ports generate IRQ/SIOSMI/SIOSCI for

wake-up events, with individual:

❏

Enable control

❏

Power-off, 4-second override

Power button output

—

Sleep Button support

Polarity and edge/level selection

Debounce mechanism

—

powered

—

Low-cost external GPIO port expansion via X-Bus

(PC87416

and PC87417)

Power Supply On/Off control

—

Supports Legacy- and ACPI-compatible Power

button

—

Direct power supply control in response to wake-up

events

—

Programmable Crowbar time-out for On request

—

On/Off control via software emulation

—

Power-fail recovery

Enhanced Power Management (PM), including:

—

Special conﬁguration registers for power down

—

Reduced current leakage from pins

—

Low-power CMOS technology

—

Ability to disable all modules

Keyboard Events

—

Wake-up on any key

—

Supports programmable 8-byte sequence “pass-

word” for Power Management

—

Simultaneous recognition of three programmable

keys (sequences): “Power”, “Sleep” and “Resume”

Power Active Timers

—

Two power-on, elapsed-time counters for the main

) and standby (V

) power supplies

—

32-bit counters with 1 second LSB

—

BAT

backed-up counters

Real-Time Clock (RTC)

—

DS1287, MC146818 and PC87911 compatible

—

242-byte battery backed-up CMOS RAM in two

banks (accessed through 70-71h and 72-73h)

—

Selective lock mechanisms for the RTC RAM

—

Y2K-compliant calendar, including century and

automatic leap-year adjustment

—

Time of day in seconds, minutes and hours that al-

lows a 12-hour or 24-hour format with optional

adjustment for daylight saving time

—

BCD or binary format for timekeeping

—

Four individually maskable interrupt event ﬂags:

❏

Periodic rates from 122

µs

to 500 ms

❏

Day-of-month alarm

Time-of-day alarm

Once-per-second to once-per-day

—

Double-buffer time registers

Revision 1.2

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PC8741x

Features

(Continued)

Watchdog

—

Watchdog counter reset by:

❏

Serial Ports Interrupts

❏

Keyboard and Mouse Interrupts

Software control

—

On-chip low-frequency clock generator:

❏

32.768 KHz for RTC, System Wake-Up Control

(SWC), Power Active timers and the high-fre-

quency clock generator

❏

Very low power consumption

BAT

powered

—

8-bit counter with 1 minute LSB

—

Generates a 250 ms pulse at WDO pin

—

Programmable SIOSMI or SIOSCI events

—

On-chip high-frequency clock generator:

❏

Based on the 32.768 KHz clock

❏

Clocking, Supply and Package Information

powered

Strap Input Controlled Operating Modes

—

Base Address (BADDR) for the PnP Index-Data

—

Input clock presence (CKIN48) select

—

X-Bus conﬁguration (XCNF2-0) select (PC87413

and PC87417)

—

ACCESS.bus slave address (ACBSA) select

(PC87416

and PC87417)

—

TRI-STATE device pins (TRIS)

Clocks

—

LPC clock input (up to 33 MHz)

—

ServerI/O modules clock input: 48 MHz or no clock

—

Single 32.768 KHz crystal

—

Clock outputs:

❏

LFCKOUT: 32.768 KHz or 1 Hz

❏

HFCKOUT: 48 MHz or 40 MHz (or divided)

Protection

—

All pins are 5V tolerant and back-drive protected

(except the LPC bus pins)

—

Separate battery pin that includes an internal UL

protection resistor

—

GPIO multiplexing conﬁguration lock

Power Supply

—

3.3V supply operation

—

Separate pins for main (V

) and standby (V

)

power supplies

—

Backup battery input for RTC, SWC and Power

Active timers

—

Reduced standby power consumption

—

Very low power consumption for RTC and timers

(0.9

µA

typical) from backup battery

Package

—

128-pin PQFP

Device-Speciﬁc Information

The following table shows the main features for each device in the PC8741x family.

Function

1,2

LPC Bus Interface

X-Bus Extension

ACCESS.bus Interface

General-Purpose Input/Output Ports (GPIO)

Real Time Clock (RTC)

System Wake-Up Control (SWC)

Legacy Functional Blocks

YES

PC87413

YES

PC87414

YES

PC87416

YES

PC87417

YES

1. This Datasheet contains notes that are device speciﬁc.

2. The “not implemented” functions must not be accessed by the host/controller, because correct

operation is not guaranteed.

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Revision1.2

PC8741x

Features

(Continued)

Block Diagrams

These are the block diagrams for the remaining PC8741x devices (see page 1 for the PC87417):

PC87413

Serial

Interface Interface

ServerI/O

Clock

Serial

Port 1

Serial

Port 2

Parallel Port

Interface

IEEE 1284

Parallel Port

Floppy Drive

Interface

Floppy Disk

Controller

LPC Serial

Keyboard Mouse

Interface Interface Interface IRQ

Keyboard &

Mouse Controller

LPC Bus

Interface

Device

Configuration

BAT

System

Wake-Up Control

Power

Timers

RTC

Internal Clocks

Clock

Generator

GPIO

Ports

ACCESS.bus

Interface

Wake-Up Power SCI &

Events Control SMI

Low-F High-F

32.768 KHz Clock Clock

I/O

Ports

Clock Serial

Data

PC87414

Serial

Interface Interface

ServerI/O

Clock

Serial

Port 1

Serial

Port 2

Parallel Port

Interface

IEEE 1284

Parallel Port

Floppy Drive

Interface

Floppy Disk

Controller

LPC Serial

Keyboard Mouse

Interface Interface Interface IRQ

Keyboard &

Mouse Controller

LPC Bus

Interface

Device

Configuration

BAT

System

Wake-Up Control

Power

Timers

RTC

Internal Clocks

Clock

Generator

GPIO

Ports

Wake-Up Power SCI &

Events Control SMI

Low-F High-F

32.768 KHz Clock Clock

I/O

Ports

PC87416

Serial

Interface Interface

ServerI/O

Clock

Serial

Port 1

Serial

Port 2

Parallel Port

Interface

IEEE 1284

Parallel Port

Floppy Drive

Interface

Floppy Disk

Controller

LPC Serial

Keyboard Mouse

Interface Interface Interface IRQ

Keyboard &

Mouse Controller

LPC Bus

Interface

Device

Configuration

BAT

System

Wake-Up Control

Power

Timers

RTC

Internal Clocks

Clock

Generator

GPIO

Ports

X-Bus

Extension

Wake-Up Power SCI &

Events Control SMI

Low-F High-F

32.768 KHz Clock Clock

X-Bus XIRQ

I/O

Ports Interface

Revision 1.2

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